Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2802267	12453	0	0
intr_enable_rd_A	2802267	1970	0	0
reset_en_rd_A	2802267	1024	0	0
reset_en_regwen_rd_A	2802267	1084	0	0
wake_info_capture_dis_rd_A	2802267	1067	0	0
wakeup_en_rd_A	2802267	1687	0	0
wakeup_en_regwen_rd_A	2802267	908	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2802267	12453	0	0
T23	4527	8	0	0
T24	6297	8	0	0
T25	3788	237	0	0
T53	3100	32	0	0
T54	3175	27	0	0
T56	1555	150	0	0
T57	9861	8	0	0
T58	3324	123	0	0
T75	2018	46	0	0
T89	2310	20	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2802267	1970	0	0
T3	3431	9	0	0
T4	15800	0	0	0
T5	1468	0	0	0
T6	2571	0	0	0
T7	3175	0	0	0
T8	1305	0	0	0
T9	1261	0	0	0
T10	2506	0	0	0
T13	1210	0	0	0
T21	0	4	0	0
T42	1464	0	0	0
T55	0	58	0	0
T82	0	5	0	0
T83	0	2	0	0
T85	0	7	0	0
T86	0	44	0	0
T87	0	23	0	0
T120	0	79	0	0
T121	0	9	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2802267	1024	0	0
T54	3175	4	0	0
T57	9861	97	0	0
T76	3876	10	0	0
T89	2310	5	0	0
T90	2294	20	0	0
T99	1933	7	0	0
T100	1427	4	0	0
T105	2015	11	0	0
T122	4551	135	0	0
T123	1970	13	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2802267	1084	0	0
T54	3175	7	0	0
T57	9861	58	0	0
T76	3876	8	0	0
T89	2310	4	0	0
T90	2294	29	0	0
T99	1933	5	0	0
T100	1427	1	0	0
T105	2015	8	0	0
T122	4551	90	0	0
T123	1970	25	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2802267	1067	0	0
T57	9861	79	0	0
T65	10803	20	0	0
T76	3876	8	0	0
T89	2310	4	0	0
T90	2294	9	0	0
T99	1933	8	0	0
T105	2015	9	0	0
T122	4551	119	0	0
T123	1970	17	0	0
T124	3151	47	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2802267	1687	0	0
T54	3175	12	0	0
T57	9861	203	0	0
T76	3876	2	0	0
T89	2310	5	0	0
T90	2294	21	0	0
T99	1933	22	0	0
T100	1427	1	0	0
T105	2015	4	0	0
T122	4551	109	0	0
T123	1970	46	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2802267	908	0	0
T54	3175	10	0	0
T57	9861	63	0	0
T76	3876	17	0	0
T89	2310	10	0	0
T90	2294	13	0	0
T99	1933	2	0	0
T100	1427	5	0	0
T105	2015	11	0	0
T122	4551	101	0	0
T123	1970	18	0	0