Unified Coverage Report :: Module :: prim_lc_sync

Module : prim_lc_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_lc_sync_dft_en	100.00	100.00					100.00
tb.dut.u_prim_lc_sync_hw_debug_en	100.00	100.00					100.00

---

Module Instance : tb.dut.u_prim_lc_sync_dft_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_lc_sync_hw_debug_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

Line Coverage for Module : prim_lc_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Assert Coverage for Module : prim_lc_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1130	1130	0	0
OutputsKnown_A	4429042	4112852	0	0
gen_flops.OutputDelay_A	4429042	4100162	0	3390

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T7	2	2	0	0
T8	2	2	0	0
T9	2	2	0	0
T10	2	2	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4429042	4112852	0	0
T1	5708	5540	0	0
T2	30284	17812	0	0
T3	6862	6692	0	0
T4	31600	31434	0	0
T5	2936	2302	0	0
T6	5142	4636	0	0
T7	6350	4534	0	0
T8	2610	1634	0	0
T9	2522	2356	0	0
T10	5012	4836	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4429042	4100162	0	3390
T1	5708	5534	0	6
T2	30284	17326	0	6
T3	6862	6686	0	6
T4	31600	31428	0	6
T5	2936	2272	0	6
T6	5142	4618	0	6
T7	6350	4462	0	6
T8	2610	1598	0	6
T9	2522	2350	0	6
T10	5012	4830	0	6

Line Coverage for Instance : tb.dut.u_prim_lc_sync_dft_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_lc_sync_dft_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	565	565	0	0
OutputsKnown_A	2214521	2056426	0	0
gen_flops.OutputDelay_A	2214521	2050081	0	1695

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	565	565	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2214521	2056426	0	0
T1	2854	2770	0	0
T2	15142	8906	0	0
T3	3431	3346	0	0
T4	15800	15717	0	0
T5	1468	1151	0	0
T6	2571	2318	0	0
T7	3175	2267	0	0
T8	1305	817	0	0
T9	1261	1178	0	0
T10	2506	2418	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2214521	2050081	0	1695
T1	2854	2767	0	3
T2	15142	8663	0	3
T3	3431	3343	0	3
T4	15800	15714	0	3
T5	1468	1136	0	3
T6	2571	2309	0	3
T7	3175	2231	0	3
T8	1305	799	0	3
T9	1261	1175	0	3
T10	2506	2415	0	3

Line Coverage for Instance : tb.dut.u_prim_lc_sync_hw_debug_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_lc_sync_hw_debug_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	565	565	0	0
OutputsKnown_A	2214521	2056426	0	0
gen_flops.OutputDelay_A	2214521	2050081	0	1695

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	565	565	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2214521	2056426	0	0
T1	2854	2770	0	0
T2	15142	8906	0	0
T3	3431	3346	0	0
T4	15800	15717	0	0
T5	1468	1151	0	0
T6	2571	2318	0	0
T7	3175	2267	0	0
T8	1305	817	0	0
T9	1261	1178	0	0
T10	2506	2418	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2214521	2050081	0	1695
T1	2854	2767	0	3
T2	15142	8663	0	3
T3	3431	3343	0	3
T4	15800	15714	0	3
T5	1468	1136	0	3
T6	2571	2309	0	3
T7	3175	2231	0	3
T8	1305	799	0	3
T9	1261	1175	0	3
T10	2506	2415	0	3