Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	6643563	9479	0	0
StatusRise_A	6643563	13074	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6643563	9479	0	0
T1	8562	6	0	0
T2	45426	180	0	0
T3	10293	9	0	0
T4	47400	3	0	0
T5	4404	12	0	0
T6	7713	0	0	0
T7	9525	54	0	0
T8	3915	0	0	0
T9	3783	3	0	0
T10	7518	6	0	0
T13	0	6	0	0
T42	0	12	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6643563	13074	0	0
T1	8562	9	0	0
T2	45426	303	0	0
T3	10293	12	0	0
T4	47400	6	0	0
T5	4404	15	0	0
T6	7713	9	0	0
T7	9525	57	0	0
T8	3915	18	0	0
T9	3783	5	0	0
T10	7518	9	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	2214521	3189	0	0
StatusRise_A	2214521	4398	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2214521	3189	0	0
T1	2854	2	0	0
T2	15142	60	0	0
T3	3431	3	0	0
T4	15800	1	0	0
T5	1468	4	0	0
T6	2571	0	0	0
T7	3175	18	0	0
T8	1305	0	0	0
T9	1261	1	0	0
T10	2506	2	0	0
T13	0	2	0	0
T42	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2214521	4398	0	0
T1	2854	3	0	0
T2	15142	101	0	0
T3	3431	4	0	0
T4	15800	2	0	0
T5	1468	5	0	0
T6	2571	3	0	0
T7	3175	19	0	0
T8	1305	6	0	0
T9	1261	2	0	0
T10	2506	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	2214521	3189	0	0
StatusRise_A	2214521	4398	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2214521	3189	0	0
T1	2854	2	0	0
T2	15142	60	0	0
T3	3431	3	0	0
T4	15800	1	0	0
T5	1468	4	0	0
T6	2571	0	0	0
T7	3175	18	0	0
T8	1305	0	0	0
T9	1261	1	0	0
T10	2506	2	0	0
T13	0	2	0	0
T42	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2214521	4398	0	0
T1	2854	3	0	0
T2	15142	101	0	0
T3	3431	4	0	0
T4	15800	2	0	0
T5	1468	5	0	0
T6	2571	3	0	0
T7	3175	19	0	0
T8	1305	6	0	0
T9	1261	2	0	0
T10	2506	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	2214521	3101	0	0
StatusRise_A	2214521	4278	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2214521	3101	0	0
T1	2854	2	0	0
T2	15142	60	0	0
T3	3431	3	0	0
T4	15800	1	0	0
T5	1468	4	0	0
T6	2571	0	0	0
T7	3175	18	0	0
T8	1305	0	0	0
T9	1261	1	0	0
T10	2506	2	0	0
T13	0	2	0	0
T42	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2214521	4278	0	0
T1	2854	3	0	0
T2	15142	101	0	0
T3	3431	4	0	0
T4	15800	2	0	0
T5	1468	5	0	0
T6	2571	3	0	0
T7	3175	19	0	0
T8	1305	6	0	0
T9	1261	1	0	0
T10	2506	3	0	0