Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	2214873	6123	0	0
EscTimeoutStoppedByClReset_A	2214521	70583	0	0
EscTimeoutTriggersReset_A	314550	300	0	0
RomAllowActiveState_A	2214521	3982	0	0
RomAllowCheckGoodState_A	2214521	4032	0	0
RomBlockActiveState_A	2214521	28641	0	0
RomBlockCheckGoodState_A	2214521	22928	0	0
RomIntgChkDisFalse_A	2214521	2031343	0	0
RomIntgChkDisTrue_A	2214521	25083	0	0
RstreqChkEsctimeout_A	2214521	1077	0	0
RstreqChkFsmterm_A	2214521	160	0	0
RstreqChkGlbesc_A	2214521	1077	0	0
RstreqChkMainpd_A	2214521	57951	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2214873	6123	0	0
T4	15801	229	0	0
T5	1469	0	0	0
T6	2571	0	0	0
T7	3176	0	0	0
T8	1306	0	0	0
T9	1262	0	0	0
T10	2507	0	0	0
T11	0	123	0	0
T13	1211	0	0	0
T18	2742	0	0	0
T42	1464	0	0	0
T45	0	230	0	0
T46	0	175	0	0
T125	0	73	0	0
T126	0	17	0	0
T127	0	45	0	0
T128	0	20	0	0
T129	0	5	0	0
T130	0	163	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2214521	70583	0	0
T1	2854	25	0	0
T2	15142	1472	0	0
T3	3431	36	0	0
T4	15800	13	0	0
T5	1468	66	0	0
T6	2571	0	0	0
T7	3175	285	0	0
T8	1305	38	0	0
T9	1261	0	0	0
T10	2506	23	0	0
T13	0	14	0	0
T42	0	67	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314550	300	0	0
T4	201	3	0	0
T5	469	0	0	0
T6	238	0	0	0
T7	1680	0	0	0
T8	482	0	0	0
T9	393	0	0	0
T10	224	0	0	0
T11	0	3	0	0
T12	0	5	0	0
T13	391	0	0	0
T18	260	0	0	0
T42	1012	0	0	0
T44	0	4	0	0
T45	0	3	0	0
T46	0	2	0	0
T125	0	2	0	0
T126	0	3	0	0
T131	0	6	0	0
T132	0	5	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2214521	3982	0	0
T1	2854	3	0	0
T2	15142	81	0	0
T3	3431	4	0	0
T4	15800	2	0	0
T5	1468	5	0	0
T6	2571	3	0	0
T7	3175	12	0	0
T8	1305	6	0	0
T9	1261	2	0	0
T10	2506	3	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2214521	4032	0	0
T1	2854	3	0	0
T2	15142	81	0	0
T3	3431	4	0	0
T4	15800	2	0	0
T5	1468	5	0	0
T6	2571	3	0	0
T7	3175	13	0	0
T8	1305	6	0	0
T9	1261	2	0	0
T10	2506	3	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2214521	28641	0	0
T30	5381	915	0	0
T31	1778	229	0	0
T32	0	228	0	0
T36	5175	0	0	0
T37	7865	0	0	0
T38	3812	0	0	0
T40	0	1233	0	0
T51	3151	0	0	0
T52	2426	0	0	0
T82	1422	0	0	0
T85	1361	0	0	0
T91	5488	0	0	0
T133	0	907	0	0
T134	0	138	0	0
T135	0	850	0	0
T136	0	8	0	0
T137	0	1159	0	0
T138	0	236	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2214521	22928	0	0
T27	0	69	0	0
T30	5381	971	0	0
T31	1778	122	0	0
T32	0	10	0	0
T36	5175	0	0	0
T37	7865	0	0	0
T38	3812	0	0	0
T40	0	1094	0	0
T51	3151	0	0	0
T52	2426	0	0	0
T82	1422	0	0	0
T85	1361	0	0	0
T91	5488	0	0	0
T133	0	1071	0	0
T134	0	58	0	0
T135	0	913	0	0
T137	0	1029	0	0
T138	0	78	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2214521	2031343	0	0
T1	2854	2770	0	0
T2	15142	8906	0	0
T3	3431	3346	0	0
T4	15800	15717	0	0
T5	1468	1151	0	0
T6	2571	2318	0	0
T7	3175	2267	0	0
T8	1305	817	0	0
T9	1261	1178	0	0
T10	2506	2418	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2214521	25083	0	0
T30	5381	424	0	0
T31	1778	108	0	0
T32	0	538	0	0
T36	5175	0	0	0
T37	7865	0	0	0
T38	3812	0	0	0
T40	0	2155	0	0
T51	3151	0	0	0
T52	2426	0	0	0
T82	1422	0	0	0
T85	1361	0	0	0
T91	5488	0	0	0
T133	0	286	0	0
T134	0	36	0	0
T135	0	187	0	0
T136	0	108	0	0
T137	0	1538	0	0
T138	0	1041	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2214521	1077	0	0
T2	15142	20	0	0
T3	3431	0	0	0
T4	15800	1	0	0
T5	1468	0	0	0
T6	2571	0	0	0
T7	3175	3	0	0
T8	1305	0	0	0
T9	1261	0	0	0
T10	2506	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	1210	0	0	0
T17	0	2	0	0
T33	0	5	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2214521	160	0	0
T2	15142	40	0	0
T3	3431	0	0	0
T4	15800	0	0	0
T5	1468	0	0	0
T6	2571	0	0	0
T7	3175	0	0	0
T8	1305	0	0	0
T9	1261	0	0	0
T10	2506	0	0	0
T13	1210	0	0	0
T19	0	40	0	0
T20	0	20	0	0
T34	0	20	0	0
T35	0	40	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2214521	1077	0	0
T2	15142	20	0	0
T3	3431	0	0	0
T4	15800	1	0	0
T5	1468	0	0	0
T6	2571	0	0	0
T7	3175	3	0	0
T8	1305	0	0	0
T9	1261	0	0	0
T10	2506	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	1210	0	0	0
T17	0	2	0	0
T33	0	5	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2214521	57951	0	0
T6	2571	6	0	0
T7	3175	88	0	0
T8	1305	23	0	0
T9	1261	0	0	0
T10	2506	0	0	0
T13	1210	0	0	0
T14	1075	0	0	0
T18	2742	15	0	0
T21	1784	0	0	0
T22	0	6	0	0
T30	0	2408	0	0
T33	0	599	0	0
T36	0	838	0	0
T37	0	122	0	0
T42	1464	0	0	0
T139	0	21	0	0