Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
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Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv


Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 64 0 64 100.00


Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
core_cp 2 0 2 100.00 100 1 1 2
io_cp 2 0 2 100.00 100 1 1 2
main_pd_n_cp 2 0 2 100.00 100 1 1 2
sleep_cp 2 0 2 100.00 100 1 1 2
usb_active_cp 2 0 2 100.00 100 1 1 2
usb_lp_cp 2 0 2 100.00 100 1 1 2


Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
control_cross 64 0 64 100.00 100 1 1 0


Summary for Variable core_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for core_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 544 1 T2 2 T4 2 T5 7
auto[1] 431 1 T5 6 T7 1 T52 4


Summary for Variable io_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for io_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 577 1 T2 2 T4 2 T5 9
auto[1] 398 1 T5 4 T7 3 T52 5


Summary for Variable main_pd_n_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for main_pd_n_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 428 1 T5 7 T7 2 T52 1
auto[1] 547 1 T2 2 T4 2 T5 6


Summary for Variable sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sleep_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 789 1 T2 1 T4 1 T5 13
auto[1] 186 1 T2 1 T4 1 T6 1


Summary for Variable usb_active_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_active_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 470 1 T5 6 T7 2 T52 4
auto[1] 505 1 T2 2 T4 2 T5 7


Summary for Variable usb_lp_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_lp_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 532 1 T2 2 T4 2 T5 6
auto[1] 443 1 T5 7 T7 2 T52 5


Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for control_cross

Bins
core_cpio_cpusb_lp_cpusb_active_cpmain_pd_n_cpsleep_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] 27 1 T5 1 T60 2 T98 1
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] 3 1 T168 1 T169 1 T170 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] 20 1 T7 1 T53 1 T13 2
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] 1 1 T7 1 - - - -
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] 33 1 T5 1 T14 1 T171 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] 5 1 T171 1 T172 1 T173 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] 79 1 T2 1 T4 1 T5 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] 53 1 T2 1 T4 1 T6 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] 24 1 T5 1 T90 1 T60 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] 7 1 T90 1 T25 1 T97 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] 34 1 T5 1 T90 2 T99 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] 8 1 T90 1 T174 1 T175 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] 17 1 T99 2 T174 1 T176 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] 3 1 T176 1 T177 1 T178 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] 22 1 T5 1 T13 2 T123 2
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] 1 1 T170 1 - - - -
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] 15 1 T123 1 T102 1 T179 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] 2 1 T179 1 T175 1 - -
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] 26 1 T14 1 T60 2 T171 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] 5 1 T171 1 T180 1 T148 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] 24 1 T53 1 T171 1 T99 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] 4 1 T181 1 T182 1 T183 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] 15 1 T7 1 T56 1 T168 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] 5 1 T7 1 T168 1 T149 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] 27 1 T13 1 T14 1 T59 2
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] 1 1 T184 1 - - - -
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] 24 1 T13 1 T57 1 T123 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] 7 1 T57 1 T185 1 T186 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] 22 1 T5 1 T7 1 T14 2
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] 1 1 T176 1 - - - -
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] 24 1 T52 1 T92 1 T25 2
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] 5 1 T52 1 T92 1 T25 2
auto[1] auto[0] auto[0] auto[0] auto[0] auto[0] 32 1 T5 1 T53 1 T92 1
auto[1] auto[0] auto[0] auto[0] auto[0] auto[1] 6 1 T53 2 T187 1 T179 1
auto[1] auto[0] auto[0] auto[0] auto[1] auto[0] 21 1 T13 1 T60 2 T99 2
auto[1] auto[0] auto[0] auto[0] auto[1] auto[1] 2 1 T188 1 T189 1 - -
auto[1] auto[0] auto[0] auto[1] auto[0] auto[0] 19 1 T51 1 T13 1 T56 1
auto[1] auto[0] auto[0] auto[1] auto[0] auto[1] 3 1 T56 1 T55 1 T178 1
auto[1] auto[0] auto[0] auto[1] auto[1] auto[0] 26 1 T13 3 T92 1 T60 1
auto[1] auto[0] auto[0] auto[1] auto[1] auto[1] 9 1 T92 1 T174 1 T190 1
auto[1] auto[0] auto[1] auto[0] auto[0] auto[0] 35 1 T51 1 T92 1 T14 2
auto[1] auto[0] auto[1] auto[0] auto[0] auto[1] 6 1 T51 1 T191 1 T192 1
auto[1] auto[0] auto[1] auto[0] auto[1] auto[0] 29 1 T5 1 T52 1 T50 1
auto[1] auto[0] auto[1] auto[0] auto[1] auto[1] 8 1 T50 1 T180 1 T193 1
auto[1] auto[0] auto[1] auto[1] auto[0] auto[0] 13 1 T7 1 T99 1 T123 1
auto[1] auto[0] auto[1] auto[1] auto[0] auto[1] 1 1 T58 1 - - - -
auto[1] auto[0] auto[1] auto[1] auto[1] auto[0] 27 1 T5 1 T13 1 T59 1
auto[1] auto[0] auto[1] auto[1] auto[1] auto[1] 3 1 T194 1 T177 1 T195 1
auto[1] auto[1] auto[0] auto[0] auto[0] auto[0] 23 1 T52 1 T181 1 T123 1
auto[1] auto[1] auto[0] auto[0] auto[0] auto[1] 2 1 T187 1 T183 1 - -
auto[1] auto[1] auto[0] auto[0] auto[1] auto[0] 20 1 T5 1 T53 1 T25 2
auto[1] auto[1] auto[0] auto[0] auto[1] auto[1] 8 1 T25 2 T181 1 T54 1
auto[1] auto[1] auto[0] auto[1] auto[0] auto[0] 17 1 T5 1 T51 1 T13 1
auto[1] auto[1] auto[0] auto[1] auto[0] auto[1] 6 1 T51 1 T194 1 T196 1
auto[1] auto[1] auto[0] auto[1] auto[1] auto[0] 16 1 T123 1 T187 1 T102 3
auto[1] auto[1] auto[0] auto[1] auto[1] auto[1] 5 1 T197 2 T198 1 T192 1
auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] 19 1 T51 1 T100 1 T60 1
auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] 5 1 T97 1 T173 1 T199 1
auto[1] auto[1] auto[1] auto[0] auto[1] auto[0] 20 1 T52 1 T13 1 T194 1
auto[1] auto[1] auto[1] auto[0] auto[1] auto[1] 3 1 T52 1 T196 1 T186 1
auto[1] auto[1] auto[1] auto[1] auto[0] auto[0] 22 1 T5 1 T59 1 T60 1
auto[1] auto[1] auto[1] auto[1] auto[0] auto[1] 4 1 T172 1 T200 1 T189 1
auto[1] auto[1] auto[1] auto[1] auto[1] auto[0] 17 1 T50 1 T90 1 T56 1
auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 4 1 T191 1 T188 1 T58 1

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