---

Detail Report for Assertions

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AlertNumCheck_A	0	0	571	571	0	0
tb.dut.AlertsKnownO_A	0	0	2182366	2028769	0	0
tb.dut.AstKnownO_A	0	0	2182366	2028769	0	0
tb.dut.ClkKnownO_A	0	0	2182366	2028769	0	0
tb.dut.ClkRatio_A	0	0	2182366	2028769	0	0
tb.dut.FpvSecCmFsmCheck_A	0	0	2182366	70	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	2182366	70	0	0
tb.dut.FpvSecCmSlowFsmCheck_A	0	0	318124	70	0	0
tb.dut.GlitchStatusPersist_A	0	0	2182366	430	0	0
tb.dut.IntrKnownO_A	0	0	2182366	2028769	0	0
tb.dut.LcKnownO_A	0	0	2182366	2028769	0	0
tb.dut.OtpKnownO_A	0	0	2182366	2028769	0	0
tb.dut.PwrmgrSecCmEscToLCReset_A	0	0	2182366	474	0	0
tb.dut.PwrmgrSecCmEscToSlowResetReq_A	0	0	318124	3100	0	0
tb.dut.PwrmgrSecCmFsmEscToResetReq_A	0	0	2182366	24006	0	0
tb.dut.RstKnownO_A	0	0	2182366	2028769	0	0
tb.dut.TlAReadyKnownO_A	0	0	2182366	2028769	0	0
tb.dut.TlDValidKnownO_A	0	0	2182366	2028769	0	0
tb.dut.clkmgr_pwrmgr_io_sva_if.StatusFall_A	0	0	2182366	3102	0	0
tb.dut.clkmgr_pwrmgr_io_sva_if.StatusRise_A	0	0	2182366	4254	0	0
tb.dut.clkmgr_pwrmgr_main_sva_if.StatusFall_A	0	0	2182366	3102	0	0
tb.dut.clkmgr_pwrmgr_main_sva_if.StatusRise_A	0	0	2182366	4254	0	0
tb.dut.clkmgr_pwrmgr_usb_sva_if.StatusFall_A	0	0	2182366	3012	0	0
tb.dut.clkmgr_pwrmgr_usb_sva_if.StatusRise_A	0	0	2182366	4122	0	0
tb.dut.intr_wakeup.IntrTKind_A	0	0	571	571	0	0
tb.dut.pwrmgr_clock_enables_sva_if.CoreClkPwrDown_A	0	0	318124	77	0	0
tb.dut.pwrmgr_clock_enables_sva_if.CoreClkPwrUp_A	0	0	318124	3416	0	0
tb.dut.pwrmgr_clock_enables_sva_if.IoClkPwrDown_A	0	0	318124	77	0	0
tb.dut.pwrmgr_clock_enables_sva_if.IoClkPwrUp_A	0	0	318124	3416	0	0
tb.dut.pwrmgr_clock_enables_sva_if.UsbClkActive_A	0	0	318124	135	0	0
tb.dut.pwrmgr_clock_enables_sva_if.UsbClkPwrDown_A	0	0	318124	77	0	0
tb.dut.pwrmgr_clock_enables_sva_if.UsbClkPwrUp_A	0	0	318124	3416	0	0
tb.dut.pwrmgr_csr_assert.TlulOOBAddrErr_A	0	0	2755588	12555	0	0
tb.dut.pwrmgr_csr_assert.intr_enable_rd_A	0	0	2755588	2505	0	0
tb.dut.pwrmgr_csr_assert.reset_en_rd_A	0	0	2755588	1507	0	0
tb.dut.pwrmgr_csr_assert.reset_en_regwen_rd_A	0	0	2755588	1306	0	0
tb.dut.pwrmgr_csr_assert.wake_info_capture_dis_rd_A	0	0	2755588	1352	0	0
tb.dut.pwrmgr_csr_assert.wakeup_en_rd_A	0	0	2755588	2280	0	0
tb.dut.pwrmgr_csr_assert.wakeup_en_regwen_rd_A	0	0	2755588	1295	0	0
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[0].LcHandshakeOff_A	0	0	2182366	147	0	0
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[0].LcHandshakeOn_A	0	0	2182366	11882	0	0
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[0].SysHandshakeOff_A	0	0	2182366	142875	0	0
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[0].SysHandshakeOn_A	0	0	2182366	11882	0	0
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[1].LcHandshakeOff_A	0	0	2182366	147	0	0
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[1].LcHandshakeOn_A	0	0	2182366	11882	0	0
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[1].SysHandshakeOff_A	0	0	2182366	142875	0	0
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[1].SysHandshakeOn_A	0	0	2182366	11882	0	0
tb.dut.pwrmgr_sec_cm_checker_assert.EscClkStopEscTimeout_A	0	0	2182725	6259	0	0
tb.dut.pwrmgr_sec_cm_checker_assert.EscTimeoutStoppedByClReset_A	0	0	2182366	73035	0	0
tb.dut.pwrmgr_sec_cm_checker_assert.EscTimeoutTriggersReset_A	0	0	318124	328	0	0
tb.dut.pwrmgr_sec_cm_checker_assert.RomAllowActiveState_A	0	0	2182366	3864	0	0
tb.dut.pwrmgr_sec_cm_checker_assert.RomAllowCheckGoodState_A	0	0	2182366	3914	0	0
tb.dut.pwrmgr_sec_cm_checker_assert.RomBlockActiveState_A	0	0	2182366	26926	0	0
tb.dut.pwrmgr_sec_cm_checker_assert.RomBlockCheckGoodState_A	0	0	2182366	16465	0	0
tb.dut.pwrmgr_sec_cm_checker_assert.RomIntgChkDisFalse_A	0	0	2182366	1999327	0	0
tb.dut.pwrmgr_sec_cm_checker_assert.RomIntgChkDisTrue_A	0	0	2182366	29442	0	0
tb.dut.pwrmgr_sec_cm_checker_assert.RstreqChkEsctimeout_A	0	0	2182366	994	0	0
tb.dut.pwrmgr_sec_cm_checker_assert.RstreqChkFsmterm_A	0	0	2182366	140	0	0
tb.dut.pwrmgr_sec_cm_checker_assert.RstreqChkGlbesc_A	0	0	2182366	994	0	0
tb.dut.pwrmgr_sec_cm_checker_assert.RstreqChkMainpd_A	0	0	2182366	46536	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	2755588	111688	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	2755588	2563838	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	2755588	2563838	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	2755588	153008	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	2755588	2563838	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	2755588	2563838	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[119].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[11].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[120].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[121].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[122].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[123].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[124].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[125].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[126].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[127].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[128].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[129].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[12].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[130].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[131].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[132].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[133].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[134].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[135].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[136].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[137].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[138].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[139].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[13].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[140].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[141].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[142].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[143].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[144].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[145].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[146].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[147].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[148].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[149].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[14].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[150].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[151].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[152].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[153].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[154].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[155].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[156].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[157].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[158].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[159].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[15].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[160].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[161].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[162].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[163].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[164].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[165].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[166].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[167].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[168].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[169].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[16].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[170].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[171].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[172].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[173].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[174].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[175].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[176].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[177].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[178].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[179].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[17].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[180].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[181].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[182].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[183].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[184].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[185].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[186].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[187].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[188].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[189].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[18].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[190].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[191].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[192].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[193].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[194].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[195].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[196].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[197].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[198].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[199].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[19].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[1].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[200].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[201].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[202].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[203].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[204].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
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tb.dut.tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
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tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A	0	0	736	736	0	0
tb.dut.tlul_assert_device.gen_device.aDataKnown_M	0	0	2756053	62896	0	0
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A	0	0	2755588	5169	0	0
tb.dut.tlul_assert_device.gen_device.contigMask_M	0	0	2756053	40690	0	0
tb.dut.tlul_assert_device.gen_device.dDataKnown_A	0	0	2756053	43342	0	0
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A	0	0	2755588	5627	0	0
tb.dut.tlul_assert_device.gen_device.legalAParam_M	0	0	2756053	111688	0	0
tb.dut.tlul_assert_device.gen_device.legalDParam_A	0	0	2756053	153010	0	0
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M	0	0	2756053	111688	0	0
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A	0	0	2756053	153010	0	0
tb.dut.tlul_assert_device.gen_device.respOpcode_A	0	0	2756053	153010	0	0
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A	0	0	2756053	153010	0	0
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A	0	0	2755588	3000	0	0
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A	0	0	2755588	2272	0	0
tb.dut.tlul_assert_device.p_dbw.TlDbw_A	0	0	736	736	0	0
tb.dut.u_cdc.u_scdc_sync.DstPulseCheck_A	0	0	2182366	2077	0	0
tb.dut.u_cdc.u_scdc_sync.SrcPulseCheck_M	0	0	318124	2106	0	0
tb.dut.u_cdc.u_slow_cdc_sync.DstPulseCheck_A	0	0	318124	2083	0	0
tb.dut.u_cdc.u_slow_cdc_sync.SrcPulseCheck_M	0	0	2182366	2166	0	0
tb.dut.u_cdc.u_sync_rom_ctrl.NumCopiesMustBeGreaterZero_A	0	0	571	571	0	0
tb.dut.u_cdc.u_sync_rom_ctrl.OutputsKnown_A	0	0	2182366	2028769	0	0
tb.dut.u_cdc.u_sync_rom_ctrl.gen_flops.gen_stable_chks.OutputDelay_A	0	0	2182366	2022643	0	1713
tb.dut.u_cdc.u_sync_rom_ctrl.gen_flops.gen_stable_chks.OutputIfUnstable_A	0	0	2182366	2765	0	0
tb.dut.u_esc_timeout.u_ref_timeout.SyncReqAckAckNeedsReq	0	0	1999439	230186	0	0
tb.dut.u_fsm.AlwaysOnIndex_A	0	0	571	571	0	0
tb.dut.u_fsm.u_state_regs.AssertConnected_A	0	0	571	571	0	0
tb.dut.u_fsm.u_state_regs_A	0	0	2182366	2028769	0	0
tb.dut.u_prim_lc_sync_dft_en.NumCopiesMustBeGreaterZero_A	0	0	571	571	0	0
tb.dut.u_prim_lc_sync_dft_en.OutputsKnown_A	0	0	2182366	2028769	0	0
tb.dut.u_prim_lc_sync_dft_en.gen_flops.OutputDelay_A	0	0	2182366	2022643	0	1713
tb.dut.u_prim_lc_sync_hw_debug_en.NumCopiesMustBeGreaterZero_A	0	0	571	571	0	0
tb.dut.u_prim_lc_sync_hw_debug_en.OutputsKnown_A	0	0	2182366	2028769	0	0
tb.dut.u_prim_lc_sync_hw_debug_en.gen_flops.OutputDelay_A	0	0	2182366	2022643	0	1713
tb.dut.u_reg.en2addrHit	0	0	2755588	57677	0	0
tb.dut.u_reg.reAfterRv	0	0	2755588	57676	0	0
tb.dut.u_reg.rePulse	0	0	2755588	31715	0	0
tb.dut.u_reg.u_chk.PayLoadWidthCheck	0	0	736	736	0	0
tb.dut.u_reg.u_reg_if.AllowedLatency_A	0	0	736	736	0	0
tb.dut.u_reg.u_reg_if.MatchedWidthAssert	0	0	736	736	0	0
tb.dut.u_reg.u_reg_if.u_err.dataWidthOnly32_A	0	0	736	736	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	736	736	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	736	736	0	0
tb.dut.u_reg.u_rsp_intg_gen.DataWidthCheck_A	0	0	736	736	0	0
tb.dut.u_reg.u_rsp_intg_gen.PayLoadWidthCheck	0	0	736	736	0	0
tb.dut.u_reg.wePulse	0	0	2755588	25961	0	0
tb.dut.u_slow_fsm.IntRstReq_A	0	0	206793	200288	0	0
tb.dut.u_slow_fsm.u_state_regs.AssertConnected_A	0	0	571	571	0	0
tb.dut.u_slow_fsm.u_state_regs_A	0	0	318124	307914	0	0

Assertions Incomplete:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_cdc.u_sync_rom_ctrl.gen_flops.gen_stable_chks.OutputDelay_A	0	0	2182366	2022643	0	1713
tb.dut.u_prim_lc_sync_dft_en.gen_flops.OutputDelay_A	0	0	2182366	2022643	0	1713
tb.dut.u_prim_lc_sync_hw_debug_en.gen_flops.OutputDelay_A	0	0	2182366	2022643	0	1713

Assertions Excluded:

ASSERTIONS	CATEGORY	SEVERITY	EXCLUSION	EXCLUDE ANNOTATION	SRC
tb.dut.u_esc_timeout.u_ref_timeout.SyncReqAckHoldReq	0	0	Excluded	[UNR] Input req_chk_i is tied to constant 0 and src_req_i to constant 1

---

Detail Report for Cover Sequences

Cover Sequences All Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	2756053	457	457	0
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	2756053	26	26	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	2756053	34	34	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	2756053	17	17	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	2756053	10	10	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	2756053	16	16	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	2756053	13	13	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	2756053	1094	1094	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	2756053	3283	3283	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	2756053	19261	19261	716

Cover Sequences First Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	2756053	457	457	0
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	2756053	26	26	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	2756053	34	34	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	2756053	17	17	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	2756053	10	10	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	2756053	16	16	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	2756053	13	13	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	2756053	1094	1094	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	2756053	3283	3283	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	2756053	19261	19261	716