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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.39 98.23 96.15 99.44 96.00 96.18 100.00 95.74


Total test records in report: 736
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T564 /workspace/coverage/default/3.pwrmgr_glitch.31766023 Aug 06 07:48:44 PM PDT 24 Aug 06 07:48:45 PM PDT 24 61688571 ps
T30 /workspace/coverage/default/3.pwrmgr_sec_cm.513111007 Aug 06 07:48:54 PM PDT 24 Aug 06 07:48:56 PM PDT 24 386346610 ps
T565 /workspace/coverage/default/13.pwrmgr_escalation_timeout.2276989628 Aug 06 07:49:39 PM PDT 24 Aug 06 07:49:40 PM PDT 24 607060591 ps
T566 /workspace/coverage/default/28.pwrmgr_disable_rom_integrity_check.2577183646 Aug 06 07:50:25 PM PDT 24 Aug 06 07:50:26 PM PDT 24 61111444 ps
T567 /workspace/coverage/default/3.pwrmgr_smoke.3753075329 Aug 06 07:48:36 PM PDT 24 Aug 06 07:48:37 PM PDT 24 31358475 ps
T568 /workspace/coverage/default/21.pwrmgr_escalation_timeout.1676307220 Aug 06 07:49:44 PM PDT 24 Aug 06 07:49:45 PM PDT 24 541813648 ps
T569 /workspace/coverage/default/0.pwrmgr_reset.1952835375 Aug 06 07:48:47 PM PDT 24 Aug 06 07:48:48 PM PDT 24 28647778 ps
T570 /workspace/coverage/default/26.pwrmgr_escalation_timeout.3886901000 Aug 06 07:50:10 PM PDT 24 Aug 06 07:50:11 PM PDT 24 299413575 ps
T571 /workspace/coverage/default/35.pwrmgr_escalation_timeout.1745088824 Aug 06 07:50:40 PM PDT 24 Aug 06 07:50:42 PM PDT 24 165370355 ps
T572 /workspace/coverage/default/3.pwrmgr_lowpower_invalid.2427888138 Aug 06 07:48:43 PM PDT 24 Aug 06 07:48:44 PM PDT 24 74522947 ps
T573 /workspace/coverage/default/0.pwrmgr_reset_invalid.3745679456 Aug 06 07:48:31 PM PDT 24 Aug 06 07:48:32 PM PDT 24 246313024 ps
T574 /workspace/coverage/default/45.pwrmgr_reset.4264844480 Aug 06 07:50:52 PM PDT 24 Aug 06 07:50:52 PM PDT 24 284859104 ps
T575 /workspace/coverage/default/4.pwrmgr_sec_cm_rstmgr_intersig_mubi.1805334021 Aug 06 07:48:55 PM PDT 24 Aug 06 07:48:56 PM PDT 24 64089932 ps
T576 /workspace/coverage/default/49.pwrmgr_aborted_low_power.2485641163 Aug 06 07:51:37 PM PDT 24 Aug 06 07:51:38 PM PDT 24 26523087 ps
T577 /workspace/coverage/default/20.pwrmgr_sec_cm_rstmgr_intersig_mubi.2847639898 Aug 06 07:49:44 PM PDT 24 Aug 06 07:49:45 PM PDT 24 52819979 ps
T578 /workspace/coverage/default/45.pwrmgr_aborted_low_power.3370036277 Aug 06 07:50:51 PM PDT 24 Aug 06 07:50:52 PM PDT 24 46732242 ps
T579 /workspace/coverage/default/42.pwrmgr_reset_invalid.1926949638 Aug 06 07:50:53 PM PDT 24 Aug 06 07:50:54 PM PDT 24 264301853 ps
T580 /workspace/coverage/default/7.pwrmgr_aborted_low_power.1299614021 Aug 06 07:48:55 PM PDT 24 Aug 06 07:48:56 PM PDT 24 101249286 ps
T581 /workspace/coverage/default/19.pwrmgr_sec_cm_rstmgr_intersig_mubi.2539486144 Aug 06 07:49:42 PM PDT 24 Aug 06 07:49:43 PM PDT 24 136934448 ps
T582 /workspace/coverage/default/2.pwrmgr_smoke.3913208701 Aug 06 07:48:30 PM PDT 24 Aug 06 07:48:31 PM PDT 24 28902751 ps
T583 /workspace/coverage/default/15.pwrmgr_escalation_timeout.619814345 Aug 06 07:49:43 PM PDT 24 Aug 06 07:49:44 PM PDT 24 624513281 ps
T584 /workspace/coverage/default/30.pwrmgr_glitch.588889688 Aug 06 07:50:27 PM PDT 24 Aug 06 07:50:27 PM PDT 24 45113808 ps
T585 /workspace/coverage/default/22.pwrmgr_smoke.4288809177 Aug 06 07:49:46 PM PDT 24 Aug 06 07:49:47 PM PDT 24 56097545 ps
T586 /workspace/coverage/default/22.pwrmgr_global_esc.581904267 Aug 06 07:49:55 PM PDT 24 Aug 06 07:49:56 PM PDT 24 50542254 ps
T587 /workspace/coverage/default/30.pwrmgr_smoke.3148569096 Aug 06 07:50:26 PM PDT 24 Aug 06 07:50:27 PM PDT 24 26580457 ps
T588 /workspace/coverage/default/39.pwrmgr_global_esc.1576927591 Aug 06 07:50:51 PM PDT 24 Aug 06 07:50:52 PM PDT 24 99503335 ps
T589 /workspace/coverage/default/25.pwrmgr_reset_invalid.2186529861 Aug 06 07:50:03 PM PDT 24 Aug 06 07:50:04 PM PDT 24 101633808 ps
T590 /workspace/coverage/default/11.pwrmgr_esc_clk_rst_malfunc.1247901332 Aug 06 07:49:32 PM PDT 24 Aug 06 07:49:32 PM PDT 24 44993154 ps
T146 /workspace/coverage/default/15.pwrmgr_lowpower_wakeup_race.1592276257 Aug 06 07:49:39 PM PDT 24 Aug 06 07:49:40 PM PDT 24 135515873 ps
T591 /workspace/coverage/default/22.pwrmgr_sec_cm_rstmgr_intersig_mubi.3507712621 Aug 06 07:49:45 PM PDT 24 Aug 06 07:49:47 PM PDT 24 50540340 ps
T592 /workspace/coverage/default/17.pwrmgr_reset.1771521082 Aug 06 07:49:47 PM PDT 24 Aug 06 07:49:48 PM PDT 24 54951226 ps
T593 /workspace/coverage/default/33.pwrmgr_esc_clk_rst_malfunc.3485936047 Aug 06 07:50:41 PM PDT 24 Aug 06 07:50:41 PM PDT 24 29827748 ps
T594 /workspace/coverage/default/40.pwrmgr_esc_clk_rst_malfunc.1837679141 Aug 06 07:50:56 PM PDT 24 Aug 06 07:50:56 PM PDT 24 38694543 ps
T595 /workspace/coverage/default/10.pwrmgr_esc_clk_rst_malfunc.1297578299 Aug 06 07:49:30 PM PDT 24 Aug 06 07:49:31 PM PDT 24 30833723 ps
T596 /workspace/coverage/default/9.pwrmgr_esc_clk_rst_malfunc.1298584939 Aug 06 07:49:28 PM PDT 24 Aug 06 07:49:28 PM PDT 24 38312651 ps
T597 /workspace/coverage/default/2.pwrmgr_escalation_timeout.3061028824 Aug 06 07:48:44 PM PDT 24 Aug 06 07:48:45 PM PDT 24 636158958 ps
T598 /workspace/coverage/default/36.pwrmgr_esc_clk_rst_malfunc.3450875642 Aug 06 07:50:44 PM PDT 24 Aug 06 07:50:45 PM PDT 24 37401481 ps
T599 /workspace/coverage/default/16.pwrmgr_esc_clk_rst_malfunc.2481242772 Aug 06 07:49:44 PM PDT 24 Aug 06 07:49:45 PM PDT 24 71957968 ps
T600 /workspace/coverage/default/34.pwrmgr_esc_clk_rst_malfunc.2826277252 Aug 06 07:50:42 PM PDT 24 Aug 06 07:50:44 PM PDT 24 29729265 ps
T601 /workspace/coverage/default/40.pwrmgr_disable_rom_integrity_check.2174015794 Aug 06 07:50:53 PM PDT 24 Aug 06 07:50:54 PM PDT 24 73764475 ps
T602 /workspace/coverage/default/6.pwrmgr_smoke.3973125459 Aug 06 07:49:00 PM PDT 24 Aug 06 07:49:01 PM PDT 24 52931804 ps
T603 /workspace/coverage/default/9.pwrmgr_smoke.2585188463 Aug 06 07:49:28 PM PDT 24 Aug 06 07:49:29 PM PDT 24 118986179 ps
T147 /workspace/coverage/default/11.pwrmgr_sec_cm_ctrl_config_regwen.558357931 Aug 06 07:49:26 PM PDT 24 Aug 06 07:49:27 PM PDT 24 112857628 ps
T604 /workspace/coverage/default/14.pwrmgr_esc_clk_rst_malfunc.2789726158 Aug 06 07:49:40 PM PDT 24 Aug 06 07:49:41 PM PDT 24 30586333 ps
T605 /workspace/coverage/default/39.pwrmgr_glitch.3255659349 Aug 06 07:50:44 PM PDT 24 Aug 06 07:50:45 PM PDT 24 55912338 ps
T606 /workspace/coverage/default/42.pwrmgr_esc_clk_rst_malfunc.4270712215 Aug 06 07:50:44 PM PDT 24 Aug 06 07:50:45 PM PDT 24 57456958 ps
T607 /workspace/coverage/default/0.pwrmgr_global_esc.1086391051 Aug 06 07:48:43 PM PDT 24 Aug 06 07:48:43 PM PDT 24 361984925 ps
T608 /workspace/coverage/default/33.pwrmgr_disable_rom_integrity_check.1832033720 Aug 06 07:50:41 PM PDT 24 Aug 06 07:50:42 PM PDT 24 65645440 ps
T609 /workspace/coverage/default/29.pwrmgr_escalation_timeout.388229224 Aug 06 07:50:24 PM PDT 24 Aug 06 07:50:25 PM PDT 24 606058954 ps
T610 /workspace/coverage/default/25.pwrmgr_disable_rom_integrity_check.3122537567 Aug 06 07:50:03 PM PDT 24 Aug 06 07:50:03 PM PDT 24 105466307 ps
T611 /workspace/coverage/default/14.pwrmgr_reset.4179116310 Aug 06 07:49:37 PM PDT 24 Aug 06 07:49:38 PM PDT 24 50461150 ps
T612 /workspace/coverage/default/17.pwrmgr_glitch.2265869077 Aug 06 07:49:51 PM PDT 24 Aug 06 07:49:51 PM PDT 24 39314912 ps
T613 /workspace/coverage/default/32.pwrmgr_sec_cm_rstmgr_intersig_mubi.105705711 Aug 06 07:50:41 PM PDT 24 Aug 06 07:50:41 PM PDT 24 96266431 ps
T614 /workspace/coverage/default/32.pwrmgr_esc_clk_rst_malfunc.928252554 Aug 06 07:50:41 PM PDT 24 Aug 06 07:50:42 PM PDT 24 103029261 ps
T615 /workspace/coverage/default/1.pwrmgr_global_esc.2890778399 Aug 06 07:48:47 PM PDT 24 Aug 06 07:48:48 PM PDT 24 95310768 ps
T616 /workspace/coverage/default/35.pwrmgr_glitch.1405646239 Aug 06 07:50:43 PM PDT 24 Aug 06 07:50:44 PM PDT 24 114297747 ps
T617 /workspace/coverage/default/17.pwrmgr_global_esc.3878241550 Aug 06 07:49:41 PM PDT 24 Aug 06 07:49:42 PM PDT 24 56459965 ps
T618 /workspace/coverage/default/27.pwrmgr_aborted_low_power.2259668265 Aug 06 07:49:57 PM PDT 24 Aug 06 07:49:58 PM PDT 24 24819247 ps
T619 /workspace/coverage/default/25.pwrmgr_aborted_low_power.3772611274 Aug 06 07:49:53 PM PDT 24 Aug 06 07:49:54 PM PDT 24 49607260 ps
T620 /workspace/coverage/default/45.pwrmgr_global_esc.3538532716 Aug 06 07:50:56 PM PDT 24 Aug 06 07:50:56 PM PDT 24 83217400 ps
T621 /workspace/coverage/default/47.pwrmgr_esc_clk_rst_malfunc.3725543792 Aug 06 07:51:00 PM PDT 24 Aug 06 07:51:01 PM PDT 24 38902068 ps
T622 /workspace/coverage/default/21.pwrmgr_esc_clk_rst_malfunc.2933669103 Aug 06 07:49:43 PM PDT 24 Aug 06 07:49:44 PM PDT 24 37668247 ps
T170 /workspace/coverage/default/38.pwrmgr_lowpower_invalid.2475814897 Aug 06 07:50:43 PM PDT 24 Aug 06 07:50:44 PM PDT 24 81975026 ps
T201 /workspace/coverage/default/14.pwrmgr_stress_all.3800179014 Aug 06 07:49:45 PM PDT 24 Aug 06 07:49:46 PM PDT 24 84502267 ps
T623 /workspace/coverage/default/22.pwrmgr_reset_invalid.2301612282 Aug 06 07:49:59 PM PDT 24 Aug 06 07:50:01 PM PDT 24 95351234 ps
T624 /workspace/coverage/default/45.pwrmgr_smoke.483031956 Aug 06 07:51:09 PM PDT 24 Aug 06 07:51:10 PM PDT 24 29495470 ps
T625 /workspace/coverage/default/32.pwrmgr_glitch.3517967901 Aug 06 07:50:37 PM PDT 24 Aug 06 07:50:37 PM PDT 24 39638568 ps
T626 /workspace/coverage/default/12.pwrmgr_reset.2325387807 Aug 06 07:49:26 PM PDT 24 Aug 06 07:49:27 PM PDT 24 50716406 ps
T627 /workspace/coverage/default/22.pwrmgr_disable_rom_integrity_check.2960748761 Aug 06 07:49:50 PM PDT 24 Aug 06 07:49:51 PM PDT 24 62557375 ps
T628 /workspace/coverage/default/49.pwrmgr_sec_cm_rstmgr_intersig_mubi.2746242231 Aug 06 07:51:18 PM PDT 24 Aug 06 07:51:19 PM PDT 24 79458770 ps
T629 /workspace/coverage/default/40.pwrmgr_stress_all.1302049146 Aug 06 07:50:44 PM PDT 24 Aug 06 07:50:45 PM PDT 24 109196716 ps
T21 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.1158359075 Aug 06 07:03:41 PM PDT 24 Aug 06 07:03:42 PM PDT 24 132329569 ps
T80 /workspace/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.989276869 Aug 06 07:03:44 PM PDT 24 Aug 06 07:03:45 PM PDT 24 72194865 ps
T77 /workspace/coverage/cover_reg_top/32.pwrmgr_intr_test.712400397 Aug 06 07:04:04 PM PDT 24 Aug 06 07:04:05 PM PDT 24 48799856 ps
T78 /workspace/coverage/cover_reg_top/21.pwrmgr_intr_test.2704577439 Aug 06 07:03:49 PM PDT 24 Aug 06 07:03:49 PM PDT 24 28214878 ps
T67 /workspace/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.2086787607 Aug 06 07:04:04 PM PDT 24 Aug 06 07:04:05 PM PDT 24 55002401 ps
T79 /workspace/coverage/cover_reg_top/2.pwrmgr_intr_test.515344305 Aug 06 07:03:40 PM PDT 24 Aug 06 07:03:41 PM PDT 24 68577613 ps
T68 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.1926281420 Aug 06 07:03:38 PM PDT 24 Aug 06 07:03:40 PM PDT 24 48269347 ps
T69 /workspace/coverage/cover_reg_top/17.pwrmgr_csr_rw.556971444 Aug 06 07:03:51 PM PDT 24 Aug 06 07:03:52 PM PDT 24 73314330 ps
T163 /workspace/coverage/cover_reg_top/6.pwrmgr_csr_rw.558392088 Aug 06 07:03:43 PM PDT 24 Aug 06 07:03:43 PM PDT 24 23285368 ps
T159 /workspace/coverage/cover_reg_top/25.pwrmgr_intr_test.545843374 Aug 06 07:03:59 PM PDT 24 Aug 06 07:04:00 PM PDT 24 20311695 ps
T164 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.1304444806 Aug 06 07:03:42 PM PDT 24 Aug 06 07:03:43 PM PDT 24 29735469 ps
T22 /workspace/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.3128786131 Aug 06 07:03:54 PM PDT 24 Aug 06 07:03:55 PM PDT 24 53390790 ps
T23 /workspace/coverage/cover_reg_top/8.pwrmgr_tl_errors.650404540 Aug 06 07:03:41 PM PDT 24 Aug 06 07:03:43 PM PDT 24 471356793 ps
T61 /workspace/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.2054539268 Aug 06 07:03:50 PM PDT 24 Aug 06 07:03:52 PM PDT 24 106854103 ps
T162 /workspace/coverage/cover_reg_top/43.pwrmgr_intr_test.4082168939 Aug 06 07:03:52 PM PDT 24 Aug 06 07:03:52 PM PDT 24 19124499 ps
T160 /workspace/coverage/cover_reg_top/22.pwrmgr_intr_test.3537629729 Aug 06 07:03:58 PM PDT 24 Aug 06 07:03:59 PM PDT 24 19805823 ps
T84 /workspace/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.777197383 Aug 06 07:03:49 PM PDT 24 Aug 06 07:03:50 PM PDT 24 41587285 ps
T119 /workspace/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.1111600268 Aug 06 07:03:43 PM PDT 24 Aug 06 07:03:44 PM PDT 24 37091022 ps
T161 /workspace/coverage/cover_reg_top/30.pwrmgr_intr_test.4245180738 Aug 06 07:04:00 PM PDT 24 Aug 06 07:04:00 PM PDT 24 29752249 ps
T106 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_rw.4263346600 Aug 06 07:03:40 PM PDT 24 Aug 06 07:03:41 PM PDT 24 50768088 ps
T630 /workspace/coverage/cover_reg_top/49.pwrmgr_intr_test.3999311456 Aug 06 07:04:10 PM PDT 24 Aug 06 07:04:11 PM PDT 24 26656606 ps
T631 /workspace/coverage/cover_reg_top/18.pwrmgr_intr_test.1549599753 Aug 06 07:03:53 PM PDT 24 Aug 06 07:03:53 PM PDT 24 59579536 ps
T64 /workspace/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.3785280386 Aug 06 07:04:08 PM PDT 24 Aug 06 07:04:09 PM PDT 24 48657829 ps
T130 /workspace/coverage/cover_reg_top/15.pwrmgr_csr_rw.3425893603 Aug 06 07:03:53 PM PDT 24 Aug 06 07:03:54 PM PDT 24 135770996 ps
T632 /workspace/coverage/cover_reg_top/46.pwrmgr_intr_test.3859856442 Aug 06 07:04:06 PM PDT 24 Aug 06 07:04:07 PM PDT 24 93728538 ps
T633 /workspace/coverage/cover_reg_top/17.pwrmgr_intr_test.3804988190 Aug 06 07:04:08 PM PDT 24 Aug 06 07:04:09 PM PDT 24 20421522 ps
T62 /workspace/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.1038909299 Aug 06 07:03:39 PM PDT 24 Aug 06 07:03:40 PM PDT 24 125969053 ps
T63 /workspace/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.3617888483 Aug 06 07:03:59 PM PDT 24 Aug 06 07:04:01 PM PDT 24 356068052 ps
T120 /workspace/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.3306481634 Aug 06 07:03:47 PM PDT 24 Aug 06 07:03:48 PM PDT 24 23141515 ps
T107 /workspace/coverage/cover_reg_top/13.pwrmgr_csr_rw.3207248362 Aug 06 07:03:53 PM PDT 24 Aug 06 07:03:54 PM PDT 24 46170081 ps
T634 /workspace/coverage/cover_reg_top/5.pwrmgr_csr_rw.3584185999 Aug 06 07:03:42 PM PDT 24 Aug 06 07:03:43 PM PDT 24 48438883 ps
T121 /workspace/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.489491285 Aug 06 07:03:41 PM PDT 24 Aug 06 07:03:42 PM PDT 24 47264434 ps
T635 /workspace/coverage/cover_reg_top/6.pwrmgr_intr_test.4090181478 Aug 06 07:03:43 PM PDT 24 Aug 06 07:03:44 PM PDT 24 33074601 ps
T65 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.4191923477 Aug 06 07:03:43 PM PDT 24 Aug 06 07:03:44 PM PDT 24 84907555 ps
T122 /workspace/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.1123347045 Aug 06 07:04:00 PM PDT 24 Aug 06 07:04:01 PM PDT 24 34340922 ps
T108 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_rw.962562010 Aug 06 07:03:43 PM PDT 24 Aug 06 07:03:44 PM PDT 24 68522939 ps
T636 /workspace/coverage/cover_reg_top/15.pwrmgr_intr_test.1369551843 Aug 06 07:03:53 PM PDT 24 Aug 06 07:03:54 PM PDT 24 53753295 ps
T637 /workspace/coverage/cover_reg_top/28.pwrmgr_intr_test.4206939382 Aug 06 07:03:52 PM PDT 24 Aug 06 07:03:52 PM PDT 24 43312111 ps
T70 /workspace/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.388563420 Aug 06 07:04:00 PM PDT 24 Aug 06 07:04:02 PM PDT 24 202966429 ps
T66 /workspace/coverage/cover_reg_top/3.pwrmgr_tl_errors.4235628401 Aug 06 07:03:42 PM PDT 24 Aug 06 07:03:43 PM PDT 24 392511237 ps
T638 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_rw.2074036424 Aug 06 07:03:38 PM PDT 24 Aug 06 07:03:39 PM PDT 24 73824547 ps
T639 /workspace/coverage/cover_reg_top/3.pwrmgr_intr_test.3840543849 Aug 06 07:03:40 PM PDT 24 Aug 06 07:03:41 PM PDT 24 51783218 ps
T81 /workspace/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.1527968243 Aug 06 07:03:54 PM PDT 24 Aug 06 07:03:56 PM PDT 24 349709655 ps
T131 /workspace/coverage/cover_reg_top/12.pwrmgr_csr_rw.38484586 Aug 06 07:03:43 PM PDT 24 Aug 06 07:03:44 PM PDT 24 21253732 ps
T82 /workspace/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.1032124235 Aug 06 07:03:42 PM PDT 24 Aug 06 07:03:43 PM PDT 24 253458405 ps
T640 /workspace/coverage/cover_reg_top/1.pwrmgr_intr_test.1338737162 Aug 06 07:03:33 PM PDT 24 Aug 06 07:03:34 PM PDT 24 40456526 ps
T71 /workspace/coverage/cover_reg_top/0.pwrmgr_tl_errors.3410769248 Aug 06 07:03:43 PM PDT 24 Aug 06 07:03:45 PM PDT 24 77884054 ps
T641 /workspace/coverage/cover_reg_top/33.pwrmgr_intr_test.4135573046 Aug 06 07:03:59 PM PDT 24 Aug 06 07:04:00 PM PDT 24 55015763 ps
T642 /workspace/coverage/cover_reg_top/19.pwrmgr_intr_test.264023368 Aug 06 07:03:49 PM PDT 24 Aug 06 07:03:49 PM PDT 24 46832484 ps
T643 /workspace/coverage/cover_reg_top/14.pwrmgr_csr_rw.1559336854 Aug 06 07:03:52 PM PDT 24 Aug 06 07:03:53 PM PDT 24 44732713 ps
T151 /workspace/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.1526684112 Aug 06 07:03:50 PM PDT 24 Aug 06 07:03:51 PM PDT 24 208449522 ps
T644 /workspace/coverage/cover_reg_top/47.pwrmgr_intr_test.2855785863 Aug 06 07:04:06 PM PDT 24 Aug 06 07:04:07 PM PDT 24 20889943 ps
T645 /workspace/coverage/cover_reg_top/4.pwrmgr_intr_test.4043063776 Aug 06 07:03:45 PM PDT 24 Aug 06 07:03:46 PM PDT 24 67796815 ps
T646 /workspace/coverage/cover_reg_top/31.pwrmgr_intr_test.886111645 Aug 06 07:03:59 PM PDT 24 Aug 06 07:04:00 PM PDT 24 56697645 ps
T109 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_rw.4074574018 Aug 06 07:03:48 PM PDT 24 Aug 06 07:03:49 PM PDT 24 79654918 ps
T87 /workspace/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.4291373115 Aug 06 07:03:58 PM PDT 24 Aug 06 07:04:00 PM PDT 24 342317854 ps
T647 /workspace/coverage/cover_reg_top/0.pwrmgr_intr_test.2670747331 Aug 06 07:03:44 PM PDT 24 Aug 06 07:03:44 PM PDT 24 147953137 ps
T648 /workspace/coverage/cover_reg_top/10.pwrmgr_intr_test.446285406 Aug 06 07:03:41 PM PDT 24 Aug 06 07:03:42 PM PDT 24 76402510 ps
T649 /workspace/coverage/cover_reg_top/37.pwrmgr_intr_test.40998122 Aug 06 07:04:00 PM PDT 24 Aug 06 07:04:00 PM PDT 24 18408352 ps
T72 /workspace/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.208464393 Aug 06 07:03:44 PM PDT 24 Aug 06 07:03:45 PM PDT 24 987691584 ps
T650 /workspace/coverage/cover_reg_top/26.pwrmgr_intr_test.46888533 Aug 06 07:03:53 PM PDT 24 Aug 06 07:03:54 PM PDT 24 44813083 ps
T73 /workspace/coverage/cover_reg_top/19.pwrmgr_tl_errors.2039842711 Aug 06 07:03:53 PM PDT 24 Aug 06 07:03:55 PM PDT 24 205931356 ps
T651 /workspace/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.3827805437 Aug 06 07:03:38 PM PDT 24 Aug 06 07:03:39 PM PDT 24 60055572 ps
T652 /workspace/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.682890292 Aug 06 07:03:37 PM PDT 24 Aug 06 07:03:38 PM PDT 24 84100244 ps
T132 /workspace/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.3354348850 Aug 06 07:03:59 PM PDT 24 Aug 06 07:04:00 PM PDT 24 42421000 ps
T653 /workspace/coverage/cover_reg_top/36.pwrmgr_intr_test.3084139988 Aug 06 07:03:59 PM PDT 24 Aug 06 07:04:00 PM PDT 24 61395141 ps
T654 /workspace/coverage/cover_reg_top/12.pwrmgr_intr_test.2285825141 Aug 06 07:03:47 PM PDT 24 Aug 06 07:03:48 PM PDT 24 56486882 ps
T655 /workspace/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.2645022185 Aug 06 07:03:43 PM PDT 24 Aug 06 07:03:44 PM PDT 24 46002010 ps
T656 /workspace/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.2481005139 Aug 06 07:03:38 PM PDT 24 Aug 06 07:03:39 PM PDT 24 518822666 ps
T115 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.4083019654 Aug 06 07:03:39 PM PDT 24 Aug 06 07:03:41 PM PDT 24 65543348 ps
T657 /workspace/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.2523639722 Aug 06 07:03:42 PM PDT 24 Aug 06 07:03:43 PM PDT 24 46119738 ps
T110 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.2804612813 Aug 06 07:03:37 PM PDT 24 Aug 06 07:03:38 PM PDT 24 27468584 ps
T111 /workspace/coverage/cover_reg_top/18.pwrmgr_csr_rw.715446873 Aug 06 07:04:08 PM PDT 24 Aug 06 07:04:09 PM PDT 24 22691431 ps
T658 /workspace/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.273761951 Aug 06 07:03:53 PM PDT 24 Aug 06 07:03:54 PM PDT 24 74096568 ps
T659 /workspace/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.2550905742 Aug 06 07:03:59 PM PDT 24 Aug 06 07:04:02 PM PDT 24 275858735 ps
T660 /workspace/coverage/cover_reg_top/11.pwrmgr_intr_test.1387240178 Aug 06 07:03:40 PM PDT 24 Aug 06 07:03:41 PM PDT 24 28272863 ps
T661 /workspace/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.3443124968 Aug 06 07:03:41 PM PDT 24 Aug 06 07:03:41 PM PDT 24 44871225 ps
T662 /workspace/coverage/cover_reg_top/11.pwrmgr_csr_rw.2398098753 Aug 06 07:03:34 PM PDT 24 Aug 06 07:03:35 PM PDT 24 46517153 ps
T85 /workspace/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.21897307 Aug 06 07:03:49 PM PDT 24 Aug 06 07:03:50 PM PDT 24 183597208 ps
T663 /workspace/coverage/cover_reg_top/16.pwrmgr_intr_test.3521072487 Aug 06 07:03:53 PM PDT 24 Aug 06 07:03:54 PM PDT 24 20577351 ps
T664 /workspace/coverage/cover_reg_top/35.pwrmgr_intr_test.1105938177 Aug 06 07:04:08 PM PDT 24 Aug 06 07:04:09 PM PDT 24 45164175 ps
T74 /workspace/coverage/cover_reg_top/2.pwrmgr_tl_errors.1007879678 Aug 06 07:03:38 PM PDT 24 Aug 06 07:03:39 PM PDT 24 214958041 ps
T75 /workspace/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.421035113 Aug 06 07:03:40 PM PDT 24 Aug 06 07:03:42 PM PDT 24 1767614165 ps
T112 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.3970019040 Aug 06 07:03:41 PM PDT 24 Aug 06 07:03:42 PM PDT 24 52216519 ps
T665 /workspace/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.1367764267 Aug 06 07:03:41 PM PDT 24 Aug 06 07:03:43 PM PDT 24 177367555 ps
T666 /workspace/coverage/cover_reg_top/8.pwrmgr_csr_rw.3653624840 Aug 06 07:03:39 PM PDT 24 Aug 06 07:03:40 PM PDT 24 44540487 ps
T667 /workspace/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.3512889381 Aug 06 07:03:38 PM PDT 24 Aug 06 07:03:39 PM PDT 24 28631361 ps
T76 /workspace/coverage/cover_reg_top/16.pwrmgr_tl_errors.540381537 Aug 06 07:03:53 PM PDT 24 Aug 06 07:03:56 PM PDT 24 129017701 ps
T86 /workspace/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.3157126554 Aug 06 07:03:49 PM PDT 24 Aug 06 07:03:50 PM PDT 24 49076893 ps
T668 /workspace/coverage/cover_reg_top/10.pwrmgr_tl_errors.1581501060 Aug 06 07:03:40 PM PDT 24 Aug 06 07:03:43 PM PDT 24 628053084 ps
T669 /workspace/coverage/cover_reg_top/5.pwrmgr_tl_errors.2521954050 Aug 06 07:03:43 PM PDT 24 Aug 06 07:03:45 PM PDT 24 36730543 ps
T670 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.3656058564 Aug 06 07:03:40 PM PDT 24 Aug 06 07:03:40 PM PDT 24 48933812 ps
T671 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.3727424314 Aug 06 07:03:44 PM PDT 24 Aug 06 07:03:45 PM PDT 24 26952442 ps
T672 /workspace/coverage/cover_reg_top/13.pwrmgr_intr_test.1168487420 Aug 06 07:04:11 PM PDT 24 Aug 06 07:04:12 PM PDT 24 36640007 ps
T673 /workspace/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.2517964081 Aug 06 07:03:48 PM PDT 24 Aug 06 07:03:48 PM PDT 24 30750849 ps
T674 /workspace/coverage/cover_reg_top/45.pwrmgr_intr_test.1515292118 Aug 06 07:04:09 PM PDT 24 Aug 06 07:04:10 PM PDT 24 18297592 ps
T675 /workspace/coverage/cover_reg_top/24.pwrmgr_intr_test.3922066742 Aug 06 07:03:59 PM PDT 24 Aug 06 07:04:00 PM PDT 24 21270408 ps
T676 /workspace/coverage/cover_reg_top/48.pwrmgr_intr_test.333815664 Aug 06 07:04:06 PM PDT 24 Aug 06 07:04:06 PM PDT 24 46259873 ps
T677 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.1387356525 Aug 06 07:03:39 PM PDT 24 Aug 06 07:03:40 PM PDT 24 32949964 ps
T678 /workspace/coverage/cover_reg_top/17.pwrmgr_tl_errors.2971744983 Aug 06 07:03:53 PM PDT 24 Aug 06 07:03:55 PM PDT 24 77043730 ps
T679 /workspace/coverage/cover_reg_top/13.pwrmgr_tl_errors.2878061548 Aug 06 07:03:58 PM PDT 24 Aug 06 07:04:00 PM PDT 24 359946235 ps
T680 /workspace/coverage/cover_reg_top/10.pwrmgr_csr_rw.958416638 Aug 06 07:03:40 PM PDT 24 Aug 06 07:03:41 PM PDT 24 19322874 ps
T113 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.242382662 Aug 06 07:03:40 PM PDT 24 Aug 06 07:03:41 PM PDT 24 35946666 ps
T681 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.3333362797 Aug 06 07:03:35 PM PDT 24 Aug 06 07:03:36 PM PDT 24 149131569 ps
T682 /workspace/coverage/cover_reg_top/4.pwrmgr_tl_errors.3425379429 Aug 06 07:03:44 PM PDT 24 Aug 06 07:03:47 PM PDT 24 86538995 ps
T150 /workspace/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.600808759 Aug 06 07:03:41 PM PDT 24 Aug 06 07:03:42 PM PDT 24 192635538 ps
T683 /workspace/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.2442399323 Aug 06 07:03:59 PM PDT 24 Aug 06 07:04:00 PM PDT 24 50064070 ps
T684 /workspace/coverage/cover_reg_top/40.pwrmgr_intr_test.180681256 Aug 06 07:03:55 PM PDT 24 Aug 06 07:03:55 PM PDT 24 45599383 ps
T685 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.1881639700 Aug 06 07:03:42 PM PDT 24 Aug 06 07:03:43 PM PDT 24 278378591 ps
T686 /workspace/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.1576488894 Aug 06 07:03:34 PM PDT 24 Aug 06 07:03:35 PM PDT 24 350878702 ps
T687 /workspace/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.2302191705 Aug 06 07:03:43 PM PDT 24 Aug 06 07:03:44 PM PDT 24 90224634 ps
T688 /workspace/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.3769144458 Aug 06 07:03:48 PM PDT 24 Aug 06 07:03:49 PM PDT 24 257775722 ps
T689 /workspace/coverage/cover_reg_top/23.pwrmgr_intr_test.2651328838 Aug 06 07:03:59 PM PDT 24 Aug 06 07:04:00 PM PDT 24 46658130 ps
T690 /workspace/coverage/cover_reg_top/6.pwrmgr_tl_errors.288349316 Aug 06 07:03:40 PM PDT 24 Aug 06 07:03:41 PM PDT 24 124558257 ps
T691 /workspace/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.1451104051 Aug 06 07:03:39 PM PDT 24 Aug 06 07:03:40 PM PDT 24 41539535 ps
T692 /workspace/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.3520267532 Aug 06 07:03:49 PM PDT 24 Aug 06 07:03:50 PM PDT 24 105722940 ps
T693 /workspace/coverage/cover_reg_top/41.pwrmgr_intr_test.2998907226 Aug 06 07:03:51 PM PDT 24 Aug 06 07:03:52 PM PDT 24 19547800 ps
T694 /workspace/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.1452225998 Aug 06 07:03:39 PM PDT 24 Aug 06 07:03:40 PM PDT 24 104436959 ps
T695 /workspace/coverage/cover_reg_top/19.pwrmgr_csr_rw.3561021835 Aug 06 07:03:52 PM PDT 24 Aug 06 07:03:53 PM PDT 24 23654451 ps
T696 /workspace/coverage/cover_reg_top/8.pwrmgr_intr_test.532336024 Aug 06 07:03:38 PM PDT 24 Aug 06 07:03:39 PM PDT 24 46874843 ps
T697 /workspace/coverage/cover_reg_top/9.pwrmgr_csr_rw.2587741958 Aug 06 07:03:38 PM PDT 24 Aug 06 07:03:39 PM PDT 24 52304139 ps
T698 /workspace/coverage/cover_reg_top/7.pwrmgr_tl_errors.1202410177 Aug 06 07:03:38 PM PDT 24 Aug 06 07:03:39 PM PDT 24 180116393 ps
T699 /workspace/coverage/cover_reg_top/18.pwrmgr_tl_errors.392242304 Aug 06 07:03:58 PM PDT 24 Aug 06 07:04:00 PM PDT 24 318111089 ps
T700 /workspace/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.3865008308 Aug 06 07:03:58 PM PDT 24 Aug 06 07:04:00 PM PDT 24 204446841 ps
T701 /workspace/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.703579023 Aug 06 07:03:42 PM PDT 24 Aug 06 07:03:43 PM PDT 24 58014083 ps
T702 /workspace/coverage/cover_reg_top/20.pwrmgr_intr_test.2636382099 Aug 06 07:03:52 PM PDT 24 Aug 06 07:03:53 PM PDT 24 16581606 ps
T703 /workspace/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.536643604 Aug 06 07:03:39 PM PDT 24 Aug 06 07:03:39 PM PDT 24 60595314 ps
T114 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.2961064299 Aug 06 07:03:39 PM PDT 24 Aug 06 07:03:41 PM PDT 24 166078615 ps
T704 /workspace/coverage/cover_reg_top/11.pwrmgr_tl_errors.1246438084 Aug 06 07:03:45 PM PDT 24 Aug 06 07:03:47 PM PDT 24 373060308 ps
T705 /workspace/coverage/cover_reg_top/14.pwrmgr_intr_test.698511554 Aug 06 07:03:58 PM PDT 24 Aug 06 07:03:59 PM PDT 24 19936357 ps
T706 /workspace/coverage/cover_reg_top/15.pwrmgr_tl_errors.3234691397 Aug 06 07:04:08 PM PDT 24 Aug 06 07:04:10 PM PDT 24 38530909 ps
T707 /workspace/coverage/cover_reg_top/9.pwrmgr_intr_test.4136724005 Aug 06 07:03:40 PM PDT 24 Aug 06 07:03:41 PM PDT 24 189807919 ps
T708 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.4010855747 Aug 06 07:03:40 PM PDT 24 Aug 06 07:03:41 PM PDT 24 39647413 ps
T709 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.1774645596 Aug 06 07:03:41 PM PDT 24 Aug 06 07:03:43 PM PDT 24 161613191 ps
T710 /workspace/coverage/cover_reg_top/39.pwrmgr_intr_test.2280927079 Aug 06 07:03:59 PM PDT 24 Aug 06 07:03:59 PM PDT 24 32579321 ps
T711 /workspace/coverage/cover_reg_top/16.pwrmgr_csr_rw.3665214701 Aug 06 07:03:53 PM PDT 24 Aug 06 07:03:53 PM PDT 24 131447586 ps
T712 /workspace/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.2963670041 Aug 06 07:03:58 PM PDT 24 Aug 06 07:03:59 PM PDT 24 114415233 ps
T713 /workspace/coverage/cover_reg_top/7.pwrmgr_intr_test.428439918 Aug 06 07:03:38 PM PDT 24 Aug 06 07:03:39 PM PDT 24 53540892 ps
T714 /workspace/coverage/cover_reg_top/9.pwrmgr_tl_errors.1949569695 Aug 06 07:03:43 PM PDT 24 Aug 06 07:03:45 PM PDT 24 305956784 ps
T715 /workspace/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.2070802804 Aug 06 07:03:52 PM PDT 24 Aug 06 07:03:53 PM PDT 24 111941291 ps
T116 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.1517131292 Aug 06 07:03:39 PM PDT 24 Aug 06 07:03:41 PM PDT 24 47715202 ps
T716 /workspace/coverage/cover_reg_top/5.pwrmgr_intr_test.2428265733 Aug 06 07:03:48 PM PDT 24 Aug 06 07:03:48 PM PDT 24 17136985 ps
T717 /workspace/coverage/cover_reg_top/29.pwrmgr_intr_test.1842724265 Aug 06 07:04:08 PM PDT 24 Aug 06 07:04:09 PM PDT 24 48562894 ps
T718 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.4225609606 Aug 06 07:03:42 PM PDT 24 Aug 06 07:03:43 PM PDT 24 59178196 ps
T83 /workspace/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.2592898700 Aug 06 07:03:44 PM PDT 24 Aug 06 07:03:46 PM PDT 24 598962128 ps
T719 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.1326866709 Aug 06 07:03:39 PM PDT 24 Aug 06 07:03:40 PM PDT 24 38522272 ps
T720 /workspace/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.2882305804 Aug 06 07:03:40 PM PDT 24 Aug 06 07:03:41 PM PDT 24 31653570 ps
T721 /workspace/coverage/cover_reg_top/42.pwrmgr_intr_test.1244762322 Aug 06 07:03:53 PM PDT 24 Aug 06 07:03:54 PM PDT 24 30434405 ps
T722 /workspace/coverage/cover_reg_top/34.pwrmgr_intr_test.2323313948 Aug 06 07:03:59 PM PDT 24 Aug 06 07:04:00 PM PDT 24 16771580 ps
T117 /workspace/coverage/cover_reg_top/7.pwrmgr_csr_rw.449369280 Aug 06 07:03:42 PM PDT 24 Aug 06 07:03:43 PM PDT 24 34619629 ps
T723 /workspace/coverage/cover_reg_top/1.pwrmgr_tl_errors.4038372082 Aug 06 07:03:37 PM PDT 24 Aug 06 07:03:39 PM PDT 24 60966074 ps
T724 /workspace/coverage/cover_reg_top/12.pwrmgr_tl_errors.1041241069 Aug 06 07:03:43 PM PDT 24 Aug 06 07:03:45 PM PDT 24 344365582 ps
T725 /workspace/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.3572659041 Aug 06 07:03:53 PM PDT 24 Aug 06 07:03:54 PM PDT 24 36247004 ps
T118 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_rw.4033828624 Aug 06 07:03:40 PM PDT 24 Aug 06 07:03:41 PM PDT 24 26029919 ps
T726 /workspace/coverage/cover_reg_top/14.pwrmgr_tl_errors.2285675813 Aug 06 07:03:47 PM PDT 24 Aug 06 07:03:48 PM PDT 24 34474228 ps
T727 /workspace/coverage/cover_reg_top/27.pwrmgr_intr_test.725296358 Aug 06 07:04:00 PM PDT 24 Aug 06 07:04:01 PM PDT 24 31673034 ps
T728 /workspace/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.1096011236 Aug 06 07:03:44 PM PDT 24 Aug 06 07:03:45 PM PDT 24 24634328 ps
T729 /workspace/coverage/cover_reg_top/38.pwrmgr_intr_test.119604147 Aug 06 07:04:00 PM PDT 24 Aug 06 07:04:00 PM PDT 24 18177252 ps
T730 /workspace/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.2588048745 Aug 06 07:03:42 PM PDT 24 Aug 06 07:03:43 PM PDT 24 245826576 ps
T731 /workspace/coverage/cover_reg_top/44.pwrmgr_intr_test.1310762471 Aug 06 07:03:49 PM PDT 24 Aug 06 07:03:50 PM PDT 24 40823746 ps
T732 /workspace/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.1635114930 Aug 06 07:03:43 PM PDT 24 Aug 06 07:03:44 PM PDT 24 66970623 ps
T733 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.2092037741 Aug 06 07:03:42 PM PDT 24 Aug 06 07:03:44 PM PDT 24 380932388 ps
T734 /workspace/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.2675791121 Aug 06 07:04:08 PM PDT 24 Aug 06 07:04:09 PM PDT 24 41524651 ps
T735 /workspace/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.1588729946 Aug 06 07:03:42 PM PDT 24 Aug 06 07:03:43 PM PDT 24 162332593 ps
T736 /workspace/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.942629493 Aug 06 07:03:39 PM PDT 24 Aug 06 07:03:40 PM PDT 24 42364477 ps

Test location /workspace/coverage/default/37.pwrmgr_smoke.2994842661
Short name T2
Test name
Test status
Simulation time 56955151 ps
CPU time 0.66 seconds
Started Aug 06 07:50:49 PM PDT 24
Finished Aug 06 07:50:50 PM PDT 24
Peak memory 198536 kb
Host smart-8d027bc6-ef39-4751-afda-d970c8369453
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994842661 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_smoke.2994842661
Directory /workspace/37.pwrmgr_smoke/latest

Test location /workspace/coverage/default/12.pwrmgr_reset_invalid.3324088828
Short name T28
Test name
Test status
Simulation time 185644961 ps
CPU time 0.77 seconds
Started Aug 06 07:49:40 PM PDT 24
Finished Aug 06 07:49:41 PM PDT 24
Peak memory 209500 kb
Host smart-b7998015-c84f-40aa-a6ca-9ed5c6e01ad5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324088828 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset_invalid.3324088828
Directory /workspace/12.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/16.pwrmgr_aborted_low_power.258851821
Short name T5
Test name
Test status
Simulation time 31885519 ps
CPU time 0.93 seconds
Started Aug 06 07:49:47 PM PDT 24
Finished Aug 06 07:49:48 PM PDT 24
Peak memory 200668 kb
Host smart-138c94f4-920c-4c26-b39a-d79d5fa6a29c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258851821 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_aborted_low_power.258851821
Directory /workspace/16.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.1158359075
Short name T21
Test name
Test status
Simulation time 132329569 ps
CPU time 0.98 seconds
Started Aug 06 07:03:41 PM PDT 24
Finished Aug 06 07:03:42 PM PDT 24
Peak memory 200376 kb
Host smart-ca163de1-cff8-41b6-9b55-66b97b94b4af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158359075 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.pwrmgr_csr_mem_rw_with_rand_reset.1158359075
Directory /workspace/0.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm.1942744830
Short name T29
Test name
Test status
Simulation time 691079964 ps
CPU time 2.23 seconds
Started Aug 06 07:48:56 PM PDT 24
Finished Aug 06 07:48:59 PM PDT 24
Peak memory 217976 kb
Host smart-546a9c43-7027-4e7e-92e0-041b2c72210b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942744830 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm.1942744830
Directory /workspace/4.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/16.pwrmgr_lowpower_invalid.1153757805
Short name T7
Test name
Test status
Simulation time 234349428 ps
CPU time 0.67 seconds
Started Aug 06 07:49:46 PM PDT 24
Finished Aug 06 07:49:47 PM PDT 24
Peak memory 201340 kb
Host smart-ffce4ad8-4059-465c-97eb-f7a3b28d2135
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153757805 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_lowpower_inval
id.1153757805
Directory /workspace/16.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/7.pwrmgr_wakeup.68793343
Short name T25
Test name
Test status
Simulation time 78983109 ps
CPU time 0.71 seconds
Started Aug 06 07:48:57 PM PDT 24
Finished Aug 06 07:48:58 PM PDT 24
Peak memory 198332 kb
Host smart-38b7515c-9f1e-4717-b44d-c654fdd40887
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68793343 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_wakeup.68793343
Directory /workspace/7.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/11.pwrmgr_disable_rom_integrity_check.3373972674
Short name T15
Test name
Test status
Simulation time 89982263 ps
CPU time 0.68 seconds
Started Aug 06 07:49:28 PM PDT 24
Finished Aug 06 07:49:29 PM PDT 24
Peak memory 198504 kb
Host smart-fe9d8273-d383-4d03-a911-f521b3038638
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373972674 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_dis
able_rom_integrity_check.3373972674
Directory /workspace/11.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/36.pwrmgr_aborted_low_power.4257970603
Short name T99
Test name
Test status
Simulation time 63782038 ps
CPU time 0.94 seconds
Started Aug 06 07:50:42 PM PDT 24
Finished Aug 06 07:50:44 PM PDT 24
Peak memory 200164 kb
Host smart-31a647ad-6877-465d-97f3-7bb9b5d65565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257970603 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_aborted_low_power.4257970603
Directory /workspace/36.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.1038909299
Short name T62
Test name
Test status
Simulation time 125969053 ps
CPU time 1.19 seconds
Started Aug 06 07:03:39 PM PDT 24
Finished Aug 06 07:03:40 PM PDT 24
Peak memory 200448 kb
Host smart-81dc2fec-5ec7-4a6f-af26-61ee10ff52da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038909299 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_intg_err
.1038909299
Directory /workspace/9.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/24.pwrmgr_aborted_low_power.1240135633
Short name T123
Test name
Test status
Simulation time 54374012 ps
CPU time 0.98 seconds
Started Aug 06 07:50:00 PM PDT 24
Finished Aug 06 07:50:01 PM PDT 24
Peak memory 200288 kb
Host smart-56e00a61-6213-4045-84b4-fe1ba0daefea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240135633 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_aborted_low_power.1240135633
Directory /workspace/24.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_intr_test.515344305
Short name T79
Test name
Test status
Simulation time 68577613 ps
CPU time 0.6 seconds
Started Aug 06 07:03:40 PM PDT 24
Finished Aug 06 07:03:41 PM PDT 24
Peak memory 195040 kb
Host smart-d0756dbf-22e8-4cf1-a44c-e418d56ef627
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515344305 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_intr_test.515344305
Directory /workspace/2.pwrmgr_intr_test/latest

Test location /workspace/coverage/default/38.pwrmgr_wakeup_reset.615613869
Short name T55
Test name
Test status
Simulation time 78497711 ps
CPU time 0.76 seconds
Started Aug 06 07:50:53 PM PDT 24
Finished Aug 06 07:50:54 PM PDT 24
Peak memory 199340 kb
Host smart-e6209b53-9a80-486d-b08b-1e7943058c74
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615613869 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_wakeup_reset.615613869
Directory /workspace/38.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_rw.4263346600
Short name T106
Test name
Test status
Simulation time 50768088 ps
CPU time 0.68 seconds
Started Aug 06 07:03:40 PM PDT 24
Finished Aug 06 07:03:41 PM PDT 24
Peak memory 195120 kb
Host smart-012b116a-5ac9-436f-8cc7-1f874cf5854a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263346600 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_rw.4263346600
Directory /workspace/2.pwrmgr_csr_rw/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm_ctrl_config_regwen.3095604037
Short name T54
Test name
Test status
Simulation time 75199504 ps
CPU time 0.81 seconds
Started Aug 06 07:48:46 PM PDT 24
Finished Aug 06 07:48:47 PM PDT 24
Peak memory 199448 kb
Host smart-3b78f87d-06e6-4571-91eb-ed9b5a2a22c3
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095604037 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_c
m_ctrl_config_regwen.3095604037
Directory /workspace/0.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/22.pwrmgr_esc_clk_rst_malfunc.3160718601
Short name T8
Test name
Test status
Simulation time 31028138 ps
CPU time 0.68 seconds
Started Aug 06 07:49:50 PM PDT 24
Finished Aug 06 07:49:51 PM PDT 24
Peak memory 197352 kb
Host smart-b2e6908f-464a-4a95-8413-8b5c59d45879
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160718601 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_esc_clk_rst
_malfunc.3160718601
Directory /workspace/22.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/23.pwrmgr_sec_cm_rstmgr_intersig_mubi.4122802626
Short name T89
Test name
Test status
Simulation time 74729229 ps
CPU time 0.92 seconds
Started Aug 06 07:49:59 PM PDT 24
Finished Aug 06 07:50:00 PM PDT 24
Peak memory 199400 kb
Host smart-26bc62ac-c329-4d09-8950-64333345e3c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122802626 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4122802626
Directory /workspace/23.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/3.pwrmgr_disable_rom_integrity_check.1807630606
Short name T137
Test name
Test status
Simulation time 135979175 ps
CPU time 0.64 seconds
Started Aug 06 07:48:44 PM PDT 24
Finished Aug 06 07:48:44 PM PDT 24
Peak memory 199132 kb
Host smart-4a855d6b-63a1-4fb2-8539-9de83f691ffb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807630606 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_disa
ble_rom_integrity_check.1807630606
Directory /workspace/3.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_tl_errors.3410769248
Short name T71
Test name
Test status
Simulation time 77884054 ps
CPU time 1.94 seconds
Started Aug 06 07:03:43 PM PDT 24
Finished Aug 06 07:03:45 PM PDT 24
Peak memory 200736 kb
Host smart-79009e7d-6819-49da-b83c-40b518001973
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410769248 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_errors.3410769248
Directory /workspace/0.pwrmgr_tl_errors/latest

Test location /workspace/coverage/default/22.pwrmgr_lowpower_invalid.1461278023
Short name T51
Test name
Test status
Simulation time 66812342 ps
CPU time 0.66 seconds
Started Aug 06 07:50:05 PM PDT 24
Finished Aug 06 07:50:05 PM PDT 24
Peak memory 201292 kb
Host smart-eb782439-4b56-4d8e-b13d-11fed12bb0e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461278023 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_lowpower_inval
id.1461278023
Directory /workspace/22.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/10.pwrmgr_disable_rom_integrity_check.1767923914
Short name T153
Test name
Test status
Simulation time 79210222 ps
CPU time 0.65 seconds
Started Aug 06 07:49:29 PM PDT 24
Finished Aug 06 07:49:30 PM PDT 24
Peak memory 198460 kb
Host smart-e98b60bf-eade-4e5f-8a68-cba05db9c765
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767923914 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_dis
able_rom_integrity_check.1767923914
Directory /workspace/10.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/12.pwrmgr_disable_rom_integrity_check.3310378806
Short name T26
Test name
Test status
Simulation time 95210303 ps
CPU time 0.62 seconds
Started Aug 06 07:49:39 PM PDT 24
Finished Aug 06 07:49:40 PM PDT 24
Peak memory 198636 kb
Host smart-02471e49-13cd-445e-96fb-f803180a61c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310378806 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_dis
able_rom_integrity_check.3310378806
Directory /workspace/12.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/33.pwrmgr_lowpower_invalid.3016812308
Short name T186
Test name
Test status
Simulation time 85266438 ps
CPU time 0.66 seconds
Started Aug 06 07:50:39 PM PDT 24
Finished Aug 06 07:50:40 PM PDT 24
Peak memory 201372 kb
Host smart-5587063c-f13d-44aa-b6cf-affe0c039454
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016812308 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_lowpower_inval
id.3016812308
Directory /workspace/33.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/4.pwrmgr_disable_rom_integrity_check.2852806289
Short name T158
Test name
Test status
Simulation time 60736923 ps
CPU time 0.65 seconds
Started Aug 06 07:48:52 PM PDT 24
Finished Aug 06 07:48:53 PM PDT 24
Peak memory 198272 kb
Host smart-325b51a5-a31e-4aee-9829-9ddd18c773ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852806289 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_disa
ble_rom_integrity_check.2852806289
Directory /workspace/4.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.4291373115
Short name T87
Test name
Test status
Simulation time 342317854 ps
CPU time 1.48 seconds
Started Aug 06 07:03:58 PM PDT 24
Finished Aug 06 07:04:00 PM PDT 24
Peak memory 200648 kb
Host smart-182fe823-526d-4c2c-a2c4-60d6f06affb8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291373115 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_intg_er
r.4291373115
Directory /workspace/16.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/5.pwrmgr_smoke.1785238731
Short name T96
Test name
Test status
Simulation time 33643853 ps
CPU time 0.71 seconds
Started Aug 06 07:48:54 PM PDT 24
Finished Aug 06 07:48:55 PM PDT 24
Peak memory 199340 kb
Host smart-463f0c1f-b475-49e7-a95d-143c754bea05
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785238731 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_smoke.1785238731
Directory /workspace/5.pwrmgr_smoke/latest

Test location /workspace/coverage/default/16.pwrmgr_sec_cm_ctrl_config_regwen.3672887708
Short name T58
Test name
Test status
Simulation time 75175093 ps
CPU time 0.67 seconds
Started Aug 06 07:49:45 PM PDT 24
Finished Aug 06 07:49:46 PM PDT 24
Peak memory 199168 kb
Host smart-ef4fd9fe-7632-4f59-9d59-b6a225748e2d
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672887708 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_
cm_ctrl_config_regwen.3672887708
Directory /workspace/16.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/20.pwrmgr_wakeup.4282737421
Short name T125
Test name
Test status
Simulation time 70694485 ps
CPU time 0.6 seconds
Started Aug 06 07:49:46 PM PDT 24
Finished Aug 06 07:49:47 PM PDT 24
Peak memory 198256 kb
Host smart-0807d55f-fda8-4e19-8845-a1b1f88c0c80
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282737421 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_wakeup.4282737421
Directory /workspace/20.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/38.pwrmgr_lowpower_invalid.2475814897
Short name T170
Test name
Test status
Simulation time 81975026 ps
CPU time 0.66 seconds
Started Aug 06 07:50:43 PM PDT 24
Finished Aug 06 07:50:44 PM PDT 24
Peak memory 201420 kb
Host smart-a94015c3-7e9e-41e7-a116-f04af3862191
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475814897 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_lowpower_inval
id.2475814897
Directory /workspace/38.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_tl_errors.1581501060
Short name T668
Test name
Test status
Simulation time 628053084 ps
CPU time 3 seconds
Started Aug 06 07:03:40 PM PDT 24
Finished Aug 06 07:03:43 PM PDT 24
Peak memory 196628 kb
Host smart-25eeb432-f17a-4440-a34a-a846a6b91107
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581501060 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_errors.1581501060
Directory /workspace/10.pwrmgr_tl_errors/latest

Test location /workspace/coverage/default/10.pwrmgr_lowpower_invalid.417739166
Short name T177
Test name
Test status
Simulation time 147568040 ps
CPU time 0.69 seconds
Started Aug 06 07:49:28 PM PDT 24
Finished Aug 06 07:49:29 PM PDT 24
Peak memory 201416 kb
Host smart-cec12140-cbfc-4a57-8d0d-010ad4acff3f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417739166 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_lowpower_invali
d.417739166
Directory /workspace/10.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/14.pwrmgr_lowpower_invalid.1463606833
Short name T172
Test name
Test status
Simulation time 42527518 ps
CPU time 0.7 seconds
Started Aug 06 07:49:46 PM PDT 24
Finished Aug 06 07:49:47 PM PDT 24
Peak memory 201244 kb
Host smart-65ad34dc-1c74-42c8-b6cc-27bbfd895e7e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463606833 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_lowpower_inval
id.1463606833
Directory /workspace/14.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/26.pwrmgr_aborted_low_power.2505045224
Short name T13
Test name
Test status
Simulation time 70334271 ps
CPU time 0.84 seconds
Started Aug 06 07:50:03 PM PDT 24
Finished Aug 06 07:50:04 PM PDT 24
Peak memory 200252 kb
Host smart-e25574f1-62cb-432c-a10c-18dceda3c542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505045224 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_aborted_low_power.2505045224
Directory /workspace/26.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/35.pwrmgr_lowpower_invalid.213317480
Short name T187
Test name
Test status
Simulation time 37003461 ps
CPU time 0.71 seconds
Started Aug 06 07:50:42 PM PDT 24
Finished Aug 06 07:50:43 PM PDT 24
Peak memory 201428 kb
Host smart-1797ec02-c461-4b9b-ba0e-95aed5dacee0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213317480 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_lowpower_invali
d.213317480
Directory /workspace/35.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_intr_test.1369551843
Short name T636
Test name
Test status
Simulation time 53753295 ps
CPU time 0.61 seconds
Started Aug 06 07:03:53 PM PDT 24
Finished Aug 06 07:03:54 PM PDT 24
Peak memory 195076 kb
Host smart-02945432-d324-4b95-8721-3d1f9d28ee49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369551843 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_intr_test.1369551843
Directory /workspace/15.pwrmgr_intr_test/latest

Test location /workspace/coverage/default/1.pwrmgr_disable_rom_integrity_check.80058614
Short name T155
Test name
Test status
Simulation time 58502245 ps
CPU time 0.71 seconds
Started Aug 06 07:48:45 PM PDT 24
Finished Aug 06 07:48:46 PM PDT 24
Peak memory 198460 kb
Host smart-85d59e8c-1f94-40cf-8ff0-5d76513e4332
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80058614 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_int
egrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_disabl
e_rom_integrity_check.80058614
Directory /workspace/1.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/1.pwrmgr_reset_invalid.2516235345
Short name T206
Test name
Test status
Simulation time 100047921 ps
CPU time 1.16 seconds
Started Aug 06 07:48:34 PM PDT 24
Finished Aug 06 07:48:35 PM PDT 24
Peak memory 209536 kb
Host smart-4dc84602-a4bf-4fe6-b6c4-63aed7fd40fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516235345 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset_invalid.2516235345
Directory /workspace/1.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/14.pwrmgr_stress_all.3800179014
Short name T201
Test name
Test status
Simulation time 84502267 ps
CPU time 0.67 seconds
Started Aug 06 07:49:45 PM PDT 24
Finished Aug 06 07:49:46 PM PDT 24
Peak memory 198568 kb
Host smart-666832ae-a0ce-4c99-b88f-8c6eed84f2b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800179014 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_stress_all.3800179014
Directory /workspace/14.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/18.pwrmgr_lowpower_invalid.2268680292
Short name T184
Test name
Test status
Simulation time 184504517 ps
CPU time 0.65 seconds
Started Aug 06 07:49:44 PM PDT 24
Finished Aug 06 07:49:45 PM PDT 24
Peak memory 201240 kb
Host smart-574baca2-0009-482f-a523-73a1102af425
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268680292 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_lowpower_inval
id.2268680292
Directory /workspace/18.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/20.pwrmgr_lowpower_invalid.2637615075
Short name T176
Test name
Test status
Simulation time 246444775 ps
CPU time 0.66 seconds
Started Aug 06 07:49:40 PM PDT 24
Finished Aug 06 07:49:41 PM PDT 24
Peak memory 201392 kb
Host smart-02de95e3-e152-4eb0-80bf-0dcd96fa139f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637615075 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_lowpower_inval
id.2637615075
Directory /workspace/20.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/21.pwrmgr_lowpower_invalid.477577824
Short name T175
Test name
Test status
Simulation time 76946317 ps
CPU time 0.67 seconds
Started Aug 06 07:49:43 PM PDT 24
Finished Aug 06 07:49:44 PM PDT 24
Peak memory 201396 kb
Host smart-16cc6956-84e8-4764-ab9e-031f8eebd8d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477577824 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_lowpower_invali
d.477577824
Directory /workspace/21.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/24.pwrmgr_lowpower_invalid.983099969
Short name T521
Test name
Test status
Simulation time 64069508 ps
CPU time 0.65 seconds
Started Aug 06 07:50:00 PM PDT 24
Finished Aug 06 07:50:00 PM PDT 24
Peak memory 201192 kb
Host smart-997ac62f-cb2b-43e1-bed6-bd226e95987e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983099969 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_lowpower_invali
d.983099969
Directory /workspace/24.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/3.pwrmgr_lowpower_invalid.2427888138
Short name T572
Test name
Test status
Simulation time 74522947 ps
CPU time 0.64 seconds
Started Aug 06 07:48:43 PM PDT 24
Finished Aug 06 07:48:44 PM PDT 24
Peak memory 201424 kb
Host smart-ad35d40d-47f2-4a65-887d-a08a9ffc8549
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427888138 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_lowpower_invali
d.2427888138
Directory /workspace/3.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/37.pwrmgr_lowpower_invalid.1933274600
Short name T188
Test name
Test status
Simulation time 85990990 ps
CPU time 0.73 seconds
Started Aug 06 07:50:42 PM PDT 24
Finished Aug 06 07:50:44 PM PDT 24
Peak memory 201384 kb
Host smart-fe383bf4-513d-4d64-8773-f12e6cff7374
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933274600 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_lowpower_inval
id.1933274600
Directory /workspace/37.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/45.pwrmgr_lowpower_invalid.2621592521
Short name T197
Test name
Test status
Simulation time 137629384 ps
CPU time 0.65 seconds
Started Aug 06 07:51:08 PM PDT 24
Finished Aug 06 07:51:09 PM PDT 24
Peak memory 201388 kb
Host smart-00941abb-838a-4f31-95bc-6c3c72708376
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621592521 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_lowpower_inval
id.2621592521
Directory /workspace/45.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.1527968243
Short name T81
Test name
Test status
Simulation time 349709655 ps
CPU time 1.91 seconds
Started Aug 06 07:03:54 PM PDT 24
Finished Aug 06 07:03:56 PM PDT 24
Peak memory 200600 kb
Host smart-60cc8d5e-39c0-43ed-b300-b26e7051cbc6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527968243 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_intg_er
r.1527968243
Directory /workspace/13.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/14.pwrmgr_glitch.729838865
Short name T9
Test name
Test status
Simulation time 112521392 ps
CPU time 0.61 seconds
Started Aug 06 07:49:42 PM PDT 24
Finished Aug 06 07:49:43 PM PDT 24
Peak memory 198168 kb
Host smart-378a6b46-62d3-4d97-abf7-660fbb505119
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729838865 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_glitch.729838865
Directory /workspace/14.pwrmgr_glitch/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.242382662
Short name T113
Test name
Test status
Simulation time 35946666 ps
CPU time 0.81 seconds
Started Aug 06 07:03:40 PM PDT 24
Finished Aug 06 07:03:41 PM PDT 24
Peak memory 197384 kb
Host smart-3e9fa8b5-43ce-4d86-b02b-9c47a6124e0c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242382662 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_aliasing.242382662
Directory /workspace/0.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.4083019654
Short name T115
Test name
Test status
Simulation time 65543348 ps
CPU time 1.65 seconds
Started Aug 06 07:03:39 PM PDT 24
Finished Aug 06 07:03:41 PM PDT 24
Peak memory 195268 kb
Host smart-9b137ab0-f3f5-44dc-b5a9-63f4e8195421
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083019654 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_bit_bash.4
083019654
Directory /workspace/0.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.3656058564
Short name T670
Test name
Test status
Simulation time 48933812 ps
CPU time 0.68 seconds
Started Aug 06 07:03:40 PM PDT 24
Finished Aug 06 07:03:40 PM PDT 24
Peak memory 198336 kb
Host smart-d2216f1c-51e4-4a3d-81b3-5811f19fca8e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656058564 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_hw_reset.3
656058564
Directory /workspace/0.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_rw.962562010
Short name T108
Test name
Test status
Simulation time 68522939 ps
CPU time 0.68 seconds
Started Aug 06 07:03:43 PM PDT 24
Finished Aug 06 07:03:44 PM PDT 24
Peak memory 195156 kb
Host smart-914f7c40-892e-4e32-aa1d-241b9665e10c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962562010 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_rw.962562010
Directory /workspace/0.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_intr_test.2670747331
Short name T647
Test name
Test status
Simulation time 147953137 ps
CPU time 0.6 seconds
Started Aug 06 07:03:44 PM PDT 24
Finished Aug 06 07:03:44 PM PDT 24
Peak memory 195020 kb
Host smart-8f5a1783-e9fa-4b02-89f2-4c94022bdd0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670747331 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_intr_test.2670747331
Directory /workspace/0.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.536643604
Short name T703
Test name
Test status
Simulation time 60595314 ps
CPU time 0.84 seconds
Started Aug 06 07:03:39 PM PDT 24
Finished Aug 06 07:03:39 PM PDT 24
Peak memory 198396 kb
Host smart-f75919cf-6c80-4530-a2fe-1fc4d9755b48
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536643604 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sam
e_csr_outstanding.536643604
Directory /workspace/0.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.208464393
Short name T72
Test name
Test status
Simulation time 987691584 ps
CPU time 1.07 seconds
Started Aug 06 07:03:44 PM PDT 24
Finished Aug 06 07:03:45 PM PDT 24
Peak memory 195408 kb
Host smart-d2203888-b279-4f0d-b704-88e59fc94107
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208464393 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_intg_err.
208464393
Directory /workspace/0.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.1926281420
Short name T68
Test name
Test status
Simulation time 48269347 ps
CPU time 0.98 seconds
Started Aug 06 07:03:38 PM PDT 24
Finished Aug 06 07:03:40 PM PDT 24
Peak memory 195068 kb
Host smart-b65cc523-019c-43c0-8de1-25c2a3e6b7ac
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926281420 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_aliasing.1
926281420
Directory /workspace/1.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.2961064299
Short name T114
Test name
Test status
Simulation time 166078615 ps
CPU time 2.03 seconds
Started Aug 06 07:03:39 PM PDT 24
Finished Aug 06 07:03:41 PM PDT 24
Peak memory 195236 kb
Host smart-aa9e6003-1c88-4b70-9e75-025a01af3ef5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961064299 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_bit_bash.2
961064299
Directory /workspace/1.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.2804612813
Short name T110
Test name
Test status
Simulation time 27468584 ps
CPU time 0.65 seconds
Started Aug 06 07:03:37 PM PDT 24
Finished Aug 06 07:03:38 PM PDT 24
Peak memory 195140 kb
Host smart-eb95c39b-6eb7-4327-9638-3c4ec423b9b7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804612813 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_hw_reset.2
804612813
Directory /workspace/1.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.1326866709
Short name T719
Test name
Test status
Simulation time 38522272 ps
CPU time 0.74 seconds
Started Aug 06 07:03:39 PM PDT 24
Finished Aug 06 07:03:40 PM PDT 24
Peak memory 195308 kb
Host smart-c08ff5a8-092d-489b-a5a7-f7f86550d2be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326866709 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.pwrmgr_csr_mem_rw_with_rand_reset.1326866709
Directory /workspace/1.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_rw.2074036424
Short name T638
Test name
Test status
Simulation time 73824547 ps
CPU time 0.61 seconds
Started Aug 06 07:03:38 PM PDT 24
Finished Aug 06 07:03:39 PM PDT 24
Peak memory 195052 kb
Host smart-725d83d8-ecf7-417b-9437-e66609bfd7dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074036424 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_rw.2074036424
Directory /workspace/1.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_intr_test.1338737162
Short name T640
Test name
Test status
Simulation time 40456526 ps
CPU time 0.57 seconds
Started Aug 06 07:03:33 PM PDT 24
Finished Aug 06 07:03:34 PM PDT 24
Peak memory 195084 kb
Host smart-7bc08860-7dbf-4b88-9791-f28a4ff2573d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338737162 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_intr_test.1338737162
Directory /workspace/1.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.3443124968
Short name T661
Test name
Test status
Simulation time 44871225 ps
CPU time 0.73 seconds
Started Aug 06 07:03:41 PM PDT 24
Finished Aug 06 07:03:41 PM PDT 24
Peak memory 195124 kb
Host smart-a6135b5e-f6a9-41f6-bcfb-4323d0455c5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443124968 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sa
me_csr_outstanding.3443124968
Directory /workspace/1.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_tl_errors.4038372082
Short name T723
Test name
Test status
Simulation time 60966074 ps
CPU time 1.52 seconds
Started Aug 06 07:03:37 PM PDT 24
Finished Aug 06 07:03:39 PM PDT 24
Peak memory 196416 kb
Host smart-ce1f6e4a-7853-4f7f-86bb-ece71b94214e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038372082 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_errors.4038372082
Directory /workspace/1.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.2481005139
Short name T656
Test name
Test status
Simulation time 518822666 ps
CPU time 1.09 seconds
Started Aug 06 07:03:38 PM PDT 24
Finished Aug 06 07:03:39 PM PDT 24
Peak memory 200680 kb
Host smart-cfb548b8-7a45-409e-9650-85337d30b165
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481005139 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_intg_err
.2481005139
Directory /workspace/1.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.2645022185
Short name T655
Test name
Test status
Simulation time 46002010 ps
CPU time 0.69 seconds
Started Aug 06 07:03:43 PM PDT 24
Finished Aug 06 07:03:44 PM PDT 24
Peak memory 195224 kb
Host smart-6ee124ef-ef14-41ea-a182-389bb6c135b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645022185 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.pwrmgr_csr_mem_rw_with_rand_reset.2645022185
Directory /workspace/10.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_csr_rw.958416638
Short name T680
Test name
Test status
Simulation time 19322874 ps
CPU time 0.63 seconds
Started Aug 06 07:03:40 PM PDT 24
Finished Aug 06 07:03:41 PM PDT 24
Peak memory 197632 kb
Host smart-054c4af6-3e2c-41ad-8486-1d6e5d7a4b03
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958416638 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_csr_rw.958416638
Directory /workspace/10.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_intr_test.446285406
Short name T648
Test name
Test status
Simulation time 76402510 ps
CPU time 0.57 seconds
Started Aug 06 07:03:41 PM PDT 24
Finished Aug 06 07:03:42 PM PDT 24
Peak memory 195084 kb
Host smart-bf63c178-eff1-4dbf-9715-42e5c922fafb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446285406 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_intr_test.446285406
Directory /workspace/10.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.1096011236
Short name T728
Test name
Test status
Simulation time 24634328 ps
CPU time 0.74 seconds
Started Aug 06 07:03:44 PM PDT 24
Finished Aug 06 07:03:45 PM PDT 24
Peak memory 197340 kb
Host smart-55c881ad-b902-4972-8aa8-09fff458beba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096011236 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_s
ame_csr_outstanding.1096011236
Directory /workspace/10.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.1576488894
Short name T686
Test name
Test status
Simulation time 350878702 ps
CPU time 1.43 seconds
Started Aug 06 07:03:34 PM PDT 24
Finished Aug 06 07:03:35 PM PDT 24
Peak memory 200560 kb
Host smart-b05c59eb-307e-4315-be2b-8cde4cb568ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576488894 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_intg_er
r.1576488894
Directory /workspace/10.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.1635114930
Short name T732
Test name
Test status
Simulation time 66970623 ps
CPU time 0.89 seconds
Started Aug 06 07:03:43 PM PDT 24
Finished Aug 06 07:03:44 PM PDT 24
Peak memory 196216 kb
Host smart-3bff01f6-c394-468b-a1db-e71bfc54b39e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635114930 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.pwrmgr_csr_mem_rw_with_rand_reset.1635114930
Directory /workspace/11.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_csr_rw.2398098753
Short name T662
Test name
Test status
Simulation time 46517153 ps
CPU time 0.61 seconds
Started Aug 06 07:03:34 PM PDT 24
Finished Aug 06 07:03:35 PM PDT 24
Peak memory 194688 kb
Host smart-06059e7e-dc45-47fd-91e0-263fb0cfec85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398098753 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_csr_rw.2398098753
Directory /workspace/11.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_intr_test.1387240178
Short name T660
Test name
Test status
Simulation time 28272863 ps
CPU time 0.59 seconds
Started Aug 06 07:03:40 PM PDT 24
Finished Aug 06 07:03:41 PM PDT 24
Peak memory 195104 kb
Host smart-c88369fc-a1a6-40e6-b106-298016f57fd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387240178 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_intr_test.1387240178
Directory /workspace/11.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.2302191705
Short name T687
Test name
Test status
Simulation time 90224634 ps
CPU time 0.81 seconds
Started Aug 06 07:03:43 PM PDT 24
Finished Aug 06 07:03:44 PM PDT 24
Peak memory 198436 kb
Host smart-0fbf568d-405e-450a-9db4-eeabc48189b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302191705 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_s
ame_csr_outstanding.2302191705
Directory /workspace/11.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_tl_errors.1246438084
Short name T704
Test name
Test status
Simulation time 373060308 ps
CPU time 1.65 seconds
Started Aug 06 07:03:45 PM PDT 24
Finished Aug 06 07:03:47 PM PDT 24
Peak memory 196360 kb
Host smart-3610a9f9-0e12-417b-b812-e8ead5ed7df2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246438084 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_errors.1246438084
Directory /workspace/11.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.1367764267
Short name T665
Test name
Test status
Simulation time 177367555 ps
CPU time 1.65 seconds
Started Aug 06 07:03:41 PM PDT 24
Finished Aug 06 07:03:43 PM PDT 24
Peak memory 200580 kb
Host smart-4e072507-8147-43e9-982c-05a479f70796
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367764267 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_intg_er
r.1367764267
Directory /workspace/11.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.777197383
Short name T84
Test name
Test status
Simulation time 41587285 ps
CPU time 0.89 seconds
Started Aug 06 07:03:49 PM PDT 24
Finished Aug 06 07:03:50 PM PDT 24
Peak memory 195288 kb
Host smart-9409e08a-786d-4ad0-8163-25a43e3cd629
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777197383 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.pwrmgr_csr_mem_rw_with_rand_reset.777197383
Directory /workspace/12.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_csr_rw.38484586
Short name T131
Test name
Test status
Simulation time 21253732 ps
CPU time 0.67 seconds
Started Aug 06 07:03:43 PM PDT 24
Finished Aug 06 07:03:44 PM PDT 24
Peak memory 197476 kb
Host smart-43383f31-d5f1-4bf2-b03e-17ae5b0d2931
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38484586 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_csr_rw.38484586
Directory /workspace/12.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_intr_test.2285825141
Short name T654
Test name
Test status
Simulation time 56486882 ps
CPU time 0.62 seconds
Started Aug 06 07:03:47 PM PDT 24
Finished Aug 06 07:03:48 PM PDT 24
Peak memory 195084 kb
Host smart-71915283-de22-4832-b573-68c7251ab1e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285825141 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_intr_test.2285825141
Directory /workspace/12.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.3306481634
Short name T120
Test name
Test status
Simulation time 23141515 ps
CPU time 0.69 seconds
Started Aug 06 07:03:47 PM PDT 24
Finished Aug 06 07:03:48 PM PDT 24
Peak memory 195116 kb
Host smart-224b0d28-51e7-48f9-98c0-0c5fc3843206
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306481634 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_s
ame_csr_outstanding.3306481634
Directory /workspace/12.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_tl_errors.1041241069
Short name T724
Test name
Test status
Simulation time 344365582 ps
CPU time 1.98 seconds
Started Aug 06 07:03:43 PM PDT 24
Finished Aug 06 07:03:45 PM PDT 24
Peak memory 197636 kb
Host smart-0833bf4f-759b-43cf-ac98-1da3106b2a62
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041241069 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_errors.1041241069
Directory /workspace/12.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.21897307
Short name T85
Test name
Test status
Simulation time 183597208 ps
CPU time 1.06 seconds
Started Aug 06 07:03:49 PM PDT 24
Finished Aug 06 07:03:50 PM PDT 24
Peak memory 200200 kb
Host smart-a996dbb7-3f2d-4ea5-aacc-9028d0b73fac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21897307 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_intg_err.21897307
Directory /workspace/12.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.273761951
Short name T658
Test name
Test status
Simulation time 74096568 ps
CPU time 0.89 seconds
Started Aug 06 07:03:53 PM PDT 24
Finished Aug 06 07:03:54 PM PDT 24
Peak memory 195280 kb
Host smart-b889b242-99c8-4d68-9eff-2776e0a8df29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273761951 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.pwrmgr_csr_mem_rw_with_rand_reset.273761951
Directory /workspace/13.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_csr_rw.3207248362
Short name T107
Test name
Test status
Simulation time 46170081 ps
CPU time 0.63 seconds
Started Aug 06 07:03:53 PM PDT 24
Finished Aug 06 07:03:54 PM PDT 24
Peak memory 197468 kb
Host smart-b04d5e38-9d9d-4a0a-b49a-ebc104bb3430
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207248362 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_csr_rw.3207248362
Directory /workspace/13.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_intr_test.1168487420
Short name T672
Test name
Test status
Simulation time 36640007 ps
CPU time 0.61 seconds
Started Aug 06 07:04:11 PM PDT 24
Finished Aug 06 07:04:12 PM PDT 24
Peak memory 195076 kb
Host smart-759b5f44-cdad-4c56-8a0d-ffef1a8d62e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168487420 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_intr_test.1168487420
Directory /workspace/13.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.2517964081
Short name T673
Test name
Test status
Simulation time 30750849 ps
CPU time 0.78 seconds
Started Aug 06 07:03:48 PM PDT 24
Finished Aug 06 07:03:48 PM PDT 24
Peak memory 195152 kb
Host smart-fdca487c-0e1e-4e88-bfca-80c104c78350
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517964081 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_s
ame_csr_outstanding.2517964081
Directory /workspace/13.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_tl_errors.2878061548
Short name T679
Test name
Test status
Simulation time 359946235 ps
CPU time 2.11 seconds
Started Aug 06 07:03:58 PM PDT 24
Finished Aug 06 07:04:00 PM PDT 24
Peak memory 196376 kb
Host smart-6d45f40f-9041-47c2-9e4c-df0317630052
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878061548 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_errors.2878061548
Directory /workspace/13.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.3157126554
Short name T86
Test name
Test status
Simulation time 49076893 ps
CPU time 0.83 seconds
Started Aug 06 07:03:49 PM PDT 24
Finished Aug 06 07:03:50 PM PDT 24
Peak memory 195208 kb
Host smart-51c2c9bb-65d9-41c4-aeef-20576ba013a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157126554 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.pwrmgr_csr_mem_rw_with_rand_reset.3157126554
Directory /workspace/14.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_csr_rw.1559336854
Short name T643
Test name
Test status
Simulation time 44732713 ps
CPU time 0.62 seconds
Started Aug 06 07:03:52 PM PDT 24
Finished Aug 06 07:03:53 PM PDT 24
Peak memory 197288 kb
Host smart-43fa235a-55ec-4930-bb3c-4b0e3c755b06
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559336854 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_csr_rw.1559336854
Directory /workspace/14.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_intr_test.698511554
Short name T705
Test name
Test status
Simulation time 19936357 ps
CPU time 0.61 seconds
Started Aug 06 07:03:58 PM PDT 24
Finished Aug 06 07:03:59 PM PDT 24
Peak memory 194960 kb
Host smart-b0791981-318f-4681-a7f2-f5f2a4e9ddb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698511554 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_intr_test.698511554
Directory /workspace/14.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.3354348850
Short name T132
Test name
Test status
Simulation time 42421000 ps
CPU time 0.94 seconds
Started Aug 06 07:03:59 PM PDT 24
Finished Aug 06 07:04:00 PM PDT 24
Peak memory 198504 kb
Host smart-9c3dcd53-c355-439e-bacb-3205b6d73eef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354348850 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_s
ame_csr_outstanding.3354348850
Directory /workspace/14.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_tl_errors.2285675813
Short name T726
Test name
Test status
Simulation time 34474228 ps
CPU time 1.06 seconds
Started Aug 06 07:03:47 PM PDT 24
Finished Aug 06 07:03:48 PM PDT 24
Peak memory 196396 kb
Host smart-ddbfd807-1104-458b-af95-82d7163432c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285675813 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_errors.2285675813
Directory /workspace/14.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.388563420
Short name T70
Test name
Test status
Simulation time 202966429 ps
CPU time 1.72 seconds
Started Aug 06 07:04:00 PM PDT 24
Finished Aug 06 07:04:02 PM PDT 24
Peak memory 200664 kb
Host smart-56928824-afa8-424c-8d51-adcbea6ec4b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388563420 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_intg_err
.388563420
Directory /workspace/14.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.2963670041
Short name T712
Test name
Test status
Simulation time 114415233 ps
CPU time 0.88 seconds
Started Aug 06 07:03:58 PM PDT 24
Finished Aug 06 07:03:59 PM PDT 24
Peak memory 200456 kb
Host smart-9c15f10b-4c3c-4932-9684-af16863360e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963670041 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.pwrmgr_csr_mem_rw_with_rand_reset.2963670041
Directory /workspace/15.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_csr_rw.3425893603
Short name T130
Test name
Test status
Simulation time 135770996 ps
CPU time 0.65 seconds
Started Aug 06 07:03:53 PM PDT 24
Finished Aug 06 07:03:54 PM PDT 24
Peak memory 197976 kb
Host smart-0a1eb3f7-d59e-463d-81a6-c87da4032576
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425893603 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_csr_rw.3425893603
Directory /workspace/15.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.1123347045
Short name T122
Test name
Test status
Simulation time 34340922 ps
CPU time 0.78 seconds
Started Aug 06 07:04:00 PM PDT 24
Finished Aug 06 07:04:01 PM PDT 24
Peak memory 197272 kb
Host smart-c4f5d058-4e45-4925-bc19-5dc34acec435
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123347045 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_s
ame_csr_outstanding.1123347045
Directory /workspace/15.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_tl_errors.3234691397
Short name T706
Test name
Test status
Simulation time 38530909 ps
CPU time 1.56 seconds
Started Aug 06 07:04:08 PM PDT 24
Finished Aug 06 07:04:10 PM PDT 24
Peak memory 196332 kb
Host smart-384f9d5b-5724-4d45-a2ef-9429e5912d1b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234691397 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_errors.3234691397
Directory /workspace/15.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.1526684112
Short name T151
Test name
Test status
Simulation time 208449522 ps
CPU time 1.02 seconds
Started Aug 06 07:03:50 PM PDT 24
Finished Aug 06 07:03:51 PM PDT 24
Peak memory 200392 kb
Host smart-cdcdcd95-d82c-416e-9a78-1759ea9d901f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526684112 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_intg_er
r.1526684112
Directory /workspace/15.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.2070802804
Short name T715
Test name
Test status
Simulation time 111941291 ps
CPU time 0.79 seconds
Started Aug 06 07:03:52 PM PDT 24
Finished Aug 06 07:03:53 PM PDT 24
Peak memory 200544 kb
Host smart-a4f289be-6de0-4277-a530-47b976a54f3a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070802804 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.pwrmgr_csr_mem_rw_with_rand_reset.2070802804
Directory /workspace/16.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_csr_rw.3665214701
Short name T711
Test name
Test status
Simulation time 131447586 ps
CPU time 0.61 seconds
Started Aug 06 07:03:53 PM PDT 24
Finished Aug 06 07:03:53 PM PDT 24
Peak memory 197300 kb
Host smart-3dea9488-d3e9-4572-af33-0ec436e805e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665214701 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_csr_rw.3665214701
Directory /workspace/16.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_intr_test.3521072487
Short name T663
Test name
Test status
Simulation time 20577351 ps
CPU time 0.61 seconds
Started Aug 06 07:03:53 PM PDT 24
Finished Aug 06 07:03:54 PM PDT 24
Peak memory 195068 kb
Host smart-d49b8e19-67d4-4fe5-aeab-6f349674eda6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521072487 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_intr_test.3521072487
Directory /workspace/16.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.2675791121
Short name T734
Test name
Test status
Simulation time 41524651 ps
CPU time 0.73 seconds
Started Aug 06 07:04:08 PM PDT 24
Finished Aug 06 07:04:09 PM PDT 24
Peak memory 197380 kb
Host smart-b5bcae66-2d4e-4d8d-8eaf-34fb6611d38e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675791121 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_s
ame_csr_outstanding.2675791121
Directory /workspace/16.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_tl_errors.540381537
Short name T76
Test name
Test status
Simulation time 129017701 ps
CPU time 2.54 seconds
Started Aug 06 07:03:53 PM PDT 24
Finished Aug 06 07:03:56 PM PDT 24
Peak memory 196480 kb
Host smart-3fa03a8d-d4d9-4467-96bd-50a7fd04e50f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540381537 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_errors.540381537
Directory /workspace/16.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.3128786131
Short name T22
Test name
Test status
Simulation time 53390790 ps
CPU time 0.69 seconds
Started Aug 06 07:03:54 PM PDT 24
Finished Aug 06 07:03:55 PM PDT 24
Peak memory 195292 kb
Host smart-5a14f494-fd0e-4a37-971b-af4451bfaf7f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128786131 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.pwrmgr_csr_mem_rw_with_rand_reset.3128786131
Directory /workspace/17.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_csr_rw.556971444
Short name T69
Test name
Test status
Simulation time 73314330 ps
CPU time 0.67 seconds
Started Aug 06 07:03:51 PM PDT 24
Finished Aug 06 07:03:52 PM PDT 24
Peak memory 195116 kb
Host smart-f06e95aa-3239-4f4e-8a76-4488bb4257e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556971444 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_csr_rw.556971444
Directory /workspace/17.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_intr_test.3804988190
Short name T633
Test name
Test status
Simulation time 20421522 ps
CPU time 0.66 seconds
Started Aug 06 07:04:08 PM PDT 24
Finished Aug 06 07:04:09 PM PDT 24
Peak memory 195044 kb
Host smart-3c02020c-42c0-495b-a1e3-487d4bdcd8ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804988190 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_intr_test.3804988190
Directory /workspace/17.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.3769144458
Short name T688
Test name
Test status
Simulation time 257775722 ps
CPU time 0.73 seconds
Started Aug 06 07:03:48 PM PDT 24
Finished Aug 06 07:03:49 PM PDT 24
Peak memory 197436 kb
Host smart-f162b22d-44b6-4b16-b7f9-f8f83d696acb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769144458 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_s
ame_csr_outstanding.3769144458
Directory /workspace/17.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_tl_errors.2971744983
Short name T678
Test name
Test status
Simulation time 77043730 ps
CPU time 1.87 seconds
Started Aug 06 07:03:53 PM PDT 24
Finished Aug 06 07:03:55 PM PDT 24
Peak memory 197608 kb
Host smart-e1b386d2-a0b7-4e64-bf96-19689dc9d503
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971744983 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_errors.2971744983
Directory /workspace/17.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.3865008308
Short name T700
Test name
Test status
Simulation time 204446841 ps
CPU time 1.61 seconds
Started Aug 06 07:03:58 PM PDT 24
Finished Aug 06 07:04:00 PM PDT 24
Peak memory 200312 kb
Host smart-4ee94e92-b055-480b-ac66-c72b37fe6e1c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865008308 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_intg_er
r.3865008308
Directory /workspace/17.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.3572659041
Short name T725
Test name
Test status
Simulation time 36247004 ps
CPU time 0.75 seconds
Started Aug 06 07:03:53 PM PDT 24
Finished Aug 06 07:03:54 PM PDT 24
Peak memory 195228 kb
Host smart-407aa376-4908-4f1c-bb90-ad55ab51e668
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572659041 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.pwrmgr_csr_mem_rw_with_rand_reset.3572659041
Directory /workspace/18.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_csr_rw.715446873
Short name T111
Test name
Test status
Simulation time 22691431 ps
CPU time 0.68 seconds
Started Aug 06 07:04:08 PM PDT 24
Finished Aug 06 07:04:09 PM PDT 24
Peak memory 197268 kb
Host smart-5f124500-5b73-4079-bebf-bfe19e45a62f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715446873 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_csr_rw.715446873
Directory /workspace/18.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_intr_test.1549599753
Short name T631
Test name
Test status
Simulation time 59579536 ps
CPU time 0.59 seconds
Started Aug 06 07:03:53 PM PDT 24
Finished Aug 06 07:03:53 PM PDT 24
Peak memory 195076 kb
Host smart-e6f04859-88fb-4ca6-9119-8a1bf2781cf4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549599753 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_intr_test.1549599753
Directory /workspace/18.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.2086787607
Short name T67
Test name
Test status
Simulation time 55002401 ps
CPU time 0.7 seconds
Started Aug 06 07:04:04 PM PDT 24
Finished Aug 06 07:04:05 PM PDT 24
Peak memory 197580 kb
Host smart-98f7b1e7-d88d-4606-af78-7992e79f7c1d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086787607 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_s
ame_csr_outstanding.2086787607
Directory /workspace/18.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_tl_errors.392242304
Short name T699
Test name
Test status
Simulation time 318111089 ps
CPU time 1.58 seconds
Started Aug 06 07:03:58 PM PDT 24
Finished Aug 06 07:04:00 PM PDT 24
Peak memory 196292 kb
Host smart-40c5d334-b7d3-40df-a03e-6c1ba6375139
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392242304 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_errors.392242304
Directory /workspace/18.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.2550905742
Short name T659
Test name
Test status
Simulation time 275858735 ps
CPU time 1.82 seconds
Started Aug 06 07:03:59 PM PDT 24
Finished Aug 06 07:04:02 PM PDT 24
Peak memory 200748 kb
Host smart-ef1f9d46-28a0-453e-b990-177ce38d4f35
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550905742 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_intg_er
r.2550905742
Directory /workspace/18.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.3785280386
Short name T64
Test name
Test status
Simulation time 48657829 ps
CPU time 1.08 seconds
Started Aug 06 07:04:08 PM PDT 24
Finished Aug 06 07:04:09 PM PDT 24
Peak memory 200552 kb
Host smart-e9e4b864-0e9a-4b7d-9193-5fb3531e3d28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785280386 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.pwrmgr_csr_mem_rw_with_rand_reset.3785280386
Directory /workspace/19.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_csr_rw.3561021835
Short name T695
Test name
Test status
Simulation time 23654451 ps
CPU time 0.66 seconds
Started Aug 06 07:03:52 PM PDT 24
Finished Aug 06 07:03:53 PM PDT 24
Peak memory 198304 kb
Host smart-c61802cf-07e6-44f1-9b4a-548ba0fae1cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561021835 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_csr_rw.3561021835
Directory /workspace/19.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_intr_test.264023368
Short name T642
Test name
Test status
Simulation time 46832484 ps
CPU time 0.59 seconds
Started Aug 06 07:03:49 PM PDT 24
Finished Aug 06 07:03:49 PM PDT 24
Peak memory 195044 kb
Host smart-c648c977-f3c2-4e16-b42d-1487b6453d06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264023368 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_intr_test.264023368
Directory /workspace/19.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.2442399323
Short name T683
Test name
Test status
Simulation time 50064070 ps
CPU time 0.78 seconds
Started Aug 06 07:03:59 PM PDT 24
Finished Aug 06 07:04:00 PM PDT 24
Peak memory 195384 kb
Host smart-52894d89-498b-41cf-a40f-ebf03eb01a2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442399323 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_s
ame_csr_outstanding.2442399323
Directory /workspace/19.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_tl_errors.2039842711
Short name T73
Test name
Test status
Simulation time 205931356 ps
CPU time 1.42 seconds
Started Aug 06 07:03:53 PM PDT 24
Finished Aug 06 07:03:55 PM PDT 24
Peak memory 196408 kb
Host smart-027d6007-e837-4740-8e8e-1c64fe3c98ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039842711 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_errors.2039842711
Directory /workspace/19.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.3617888483
Short name T63
Test name
Test status
Simulation time 356068052 ps
CPU time 1.48 seconds
Started Aug 06 07:03:59 PM PDT 24
Finished Aug 06 07:04:01 PM PDT 24
Peak memory 200908 kb
Host smart-ca14c421-24b3-43d0-a753-5c1b7f5728bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617888483 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_intg_er
r.3617888483
Directory /workspace/19.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.1517131292
Short name T116
Test name
Test status
Simulation time 47715202 ps
CPU time 1.02 seconds
Started Aug 06 07:03:39 PM PDT 24
Finished Aug 06 07:03:41 PM PDT 24
Peak memory 195064 kb
Host smart-ec288d89-c297-4163-8603-2d425ae602ea
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517131292 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_aliasing.1
517131292
Directory /workspace/2.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.3333362797
Short name T681
Test name
Test status
Simulation time 149131569 ps
CPU time 1.67 seconds
Started Aug 06 07:03:35 PM PDT 24
Finished Aug 06 07:03:36 PM PDT 24
Peak memory 195248 kb
Host smart-cb7e3b95-91f7-4817-9d81-bff6ae36315c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333362797 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_bit_bash.3
333362797
Directory /workspace/2.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.1387356525
Short name T677
Test name
Test status
Simulation time 32949964 ps
CPU time 0.7 seconds
Started Aug 06 07:03:39 PM PDT 24
Finished Aug 06 07:03:40 PM PDT 24
Peak memory 197604 kb
Host smart-b0baf0d7-9a08-432e-b004-c2e76f57007a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387356525 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_hw_reset.1
387356525
Directory /workspace/2.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.4010855747
Short name T708
Test name
Test status
Simulation time 39647413 ps
CPU time 0.9 seconds
Started Aug 06 07:03:40 PM PDT 24
Finished Aug 06 07:03:41 PM PDT 24
Peak memory 195268 kb
Host smart-13ebd56a-aba8-4a14-b875-e0af475d774a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010855747 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.pwrmgr_csr_mem_rw_with_rand_reset.4010855747
Directory /workspace/2.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.2882305804
Short name T720
Test name
Test status
Simulation time 31653570 ps
CPU time 0.78 seconds
Started Aug 06 07:03:40 PM PDT 24
Finished Aug 06 07:03:41 PM PDT 24
Peak memory 195196 kb
Host smart-90ec422f-d8ef-4162-b67f-f7c1b11b057f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882305804 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sa
me_csr_outstanding.2882305804
Directory /workspace/2.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_tl_errors.1007879678
Short name T74
Test name
Test status
Simulation time 214958041 ps
CPU time 1.76 seconds
Started Aug 06 07:03:38 PM PDT 24
Finished Aug 06 07:03:39 PM PDT 24
Peak memory 197516 kb
Host smart-56a847f7-9523-4595-b680-d263c39a213e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007879678 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_errors.1007879678
Directory /workspace/2.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.421035113
Short name T75
Test name
Test status
Simulation time 1767614165 ps
CPU time 1.66 seconds
Started Aug 06 07:03:40 PM PDT 24
Finished Aug 06 07:03:42 PM PDT 24
Peak memory 195364 kb
Host smart-45932fac-0d5e-42e2-8f8a-ac03f52af35a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421035113 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_intg_err.
421035113
Directory /workspace/2.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.pwrmgr_intr_test.2636382099
Short name T702
Test name
Test status
Simulation time 16581606 ps
CPU time 0.59 seconds
Started Aug 06 07:03:52 PM PDT 24
Finished Aug 06 07:03:53 PM PDT 24
Peak memory 195024 kb
Host smart-69bc6ad7-e1e8-479c-b5d1-ac986575df21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636382099 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.pwrmgr_intr_test.2636382099
Directory /workspace/20.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.pwrmgr_intr_test.2704577439
Short name T78
Test name
Test status
Simulation time 28214878 ps
CPU time 0.6 seconds
Started Aug 06 07:03:49 PM PDT 24
Finished Aug 06 07:03:49 PM PDT 24
Peak memory 195044 kb
Host smart-a482b5e9-055f-407b-aed8-03c739d00378
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704577439 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.pwrmgr_intr_test.2704577439
Directory /workspace/21.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.pwrmgr_intr_test.3537629729
Short name T160
Test name
Test status
Simulation time 19805823 ps
CPU time 0.66 seconds
Started Aug 06 07:03:58 PM PDT 24
Finished Aug 06 07:03:59 PM PDT 24
Peak memory 195280 kb
Host smart-acef0df3-3572-4808-bde9-8e7f4d4514f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537629729 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.pwrmgr_intr_test.3537629729
Directory /workspace/22.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.pwrmgr_intr_test.2651328838
Short name T689
Test name
Test status
Simulation time 46658130 ps
CPU time 0.65 seconds
Started Aug 06 07:03:59 PM PDT 24
Finished Aug 06 07:04:00 PM PDT 24
Peak memory 195124 kb
Host smart-337c1017-de08-4274-b079-e3f79478391e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651328838 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.pwrmgr_intr_test.2651328838
Directory /workspace/23.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.pwrmgr_intr_test.3922066742
Short name T675
Test name
Test status
Simulation time 21270408 ps
CPU time 0.6 seconds
Started Aug 06 07:03:59 PM PDT 24
Finished Aug 06 07:04:00 PM PDT 24
Peak memory 195212 kb
Host smart-825a24fd-30f7-4275-86d0-d54efd944d10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922066742 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.pwrmgr_intr_test.3922066742
Directory /workspace/24.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.pwrmgr_intr_test.545843374
Short name T159
Test name
Test status
Simulation time 20311695 ps
CPU time 0.64 seconds
Started Aug 06 07:03:59 PM PDT 24
Finished Aug 06 07:04:00 PM PDT 24
Peak memory 194956 kb
Host smart-149fecff-c5b8-4c79-9aeb-ed1a31e7a283
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545843374 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.pwrmgr_intr_test.545843374
Directory /workspace/25.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.pwrmgr_intr_test.46888533
Short name T650
Test name
Test status
Simulation time 44813083 ps
CPU time 0.6 seconds
Started Aug 06 07:03:53 PM PDT 24
Finished Aug 06 07:03:54 PM PDT 24
Peak memory 195032 kb
Host smart-0c5ace3c-b87d-4588-b3c2-1cdfea28770e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46888533 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.pwrmgr_intr_test.46888533
Directory /workspace/26.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.pwrmgr_intr_test.725296358
Short name T727
Test name
Test status
Simulation time 31673034 ps
CPU time 0.66 seconds
Started Aug 06 07:04:00 PM PDT 24
Finished Aug 06 07:04:01 PM PDT 24
Peak memory 195276 kb
Host smart-e58be224-b78c-4644-a14f-eb11e29446f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725296358 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.pwrmgr_intr_test.725296358
Directory /workspace/27.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.pwrmgr_intr_test.4206939382
Short name T637
Test name
Test status
Simulation time 43312111 ps
CPU time 0.62 seconds
Started Aug 06 07:03:52 PM PDT 24
Finished Aug 06 07:03:52 PM PDT 24
Peak memory 195024 kb
Host smart-17bb88b5-86bb-422a-84b6-e1c24b2a867f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206939382 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.pwrmgr_intr_test.4206939382
Directory /workspace/28.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.pwrmgr_intr_test.1842724265
Short name T717
Test name
Test status
Simulation time 48562894 ps
CPU time 0.62 seconds
Started Aug 06 07:04:08 PM PDT 24
Finished Aug 06 07:04:09 PM PDT 24
Peak memory 195076 kb
Host smart-5f704d65-ce08-4622-a3d1-e9ffc4127335
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842724265 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.pwrmgr_intr_test.1842724265
Directory /workspace/29.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.3727424314
Short name T671
Test name
Test status
Simulation time 26952442 ps
CPU time 0.96 seconds
Started Aug 06 07:03:44 PM PDT 24
Finished Aug 06 07:03:45 PM PDT 24
Peak memory 195052 kb
Host smart-b8ddb5bb-3861-4f84-aae3-201509a2c1bf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727424314 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_aliasing.3
727424314
Directory /workspace/3.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.1774645596
Short name T709
Test name
Test status
Simulation time 161613191 ps
CPU time 2.06 seconds
Started Aug 06 07:03:41 PM PDT 24
Finished Aug 06 07:03:43 PM PDT 24
Peak memory 195232 kb
Host smart-5ae74ed6-8e75-4258-b019-cdf854826020
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774645596 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_bit_bash.1
774645596
Directory /workspace/3.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.3970019040
Short name T112
Test name
Test status
Simulation time 52216519 ps
CPU time 0.65 seconds
Started Aug 06 07:03:41 PM PDT 24
Finished Aug 06 07:03:42 PM PDT 24
Peak memory 198328 kb
Host smart-942edb52-141d-4b4a-88e4-8046db6c69b0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970019040 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_hw_reset.3
970019040
Directory /workspace/3.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.4191923477
Short name T65
Test name
Test status
Simulation time 84907555 ps
CPU time 0.81 seconds
Started Aug 06 07:03:43 PM PDT 24
Finished Aug 06 07:03:44 PM PDT 24
Peak memory 195252 kb
Host smart-cd633b4b-59d9-443e-9af9-7756638e6b2e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191923477 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.pwrmgr_csr_mem_rw_with_rand_reset.4191923477
Directory /workspace/3.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_rw.4033828624
Short name T118
Test name
Test status
Simulation time 26029919 ps
CPU time 0.64 seconds
Started Aug 06 07:03:40 PM PDT 24
Finished Aug 06 07:03:41 PM PDT 24
Peak memory 195116 kb
Host smart-d919b927-4394-464f-bf21-748b967b95d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033828624 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_rw.4033828624
Directory /workspace/3.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_intr_test.3840543849
Short name T639
Test name
Test status
Simulation time 51783218 ps
CPU time 0.61 seconds
Started Aug 06 07:03:40 PM PDT 24
Finished Aug 06 07:03:41 PM PDT 24
Peak memory 195064 kb
Host smart-9beb103e-da83-4633-a221-f459a481604f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840543849 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_intr_test.3840543849
Directory /workspace/3.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.3520267532
Short name T692
Test name
Test status
Simulation time 105722940 ps
CPU time 0.85 seconds
Started Aug 06 07:03:49 PM PDT 24
Finished Aug 06 07:03:50 PM PDT 24
Peak memory 198400 kb
Host smart-a50e9cbe-0662-4c10-b5d4-546836a0b4f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520267532 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sa
me_csr_outstanding.3520267532
Directory /workspace/3.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_tl_errors.4235628401
Short name T66
Test name
Test status
Simulation time 392511237 ps
CPU time 1.22 seconds
Started Aug 06 07:03:42 PM PDT 24
Finished Aug 06 07:03:43 PM PDT 24
Peak memory 196240 kb
Host smart-2f891740-cc36-4214-a431-99588475c096
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235628401 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_errors.4235628401
Directory /workspace/3.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.2588048745
Short name T730
Test name
Test status
Simulation time 245826576 ps
CPU time 1.12 seconds
Started Aug 06 07:03:42 PM PDT 24
Finished Aug 06 07:03:43 PM PDT 24
Peak memory 200680 kb
Host smart-78e9316a-6358-4683-a3c0-16ca46e73f56
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588048745 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_intg_err
.2588048745
Directory /workspace/3.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.pwrmgr_intr_test.4245180738
Short name T161
Test name
Test status
Simulation time 29752249 ps
CPU time 0.6 seconds
Started Aug 06 07:04:00 PM PDT 24
Finished Aug 06 07:04:00 PM PDT 24
Peak memory 195040 kb
Host smart-d32458b7-203a-4dff-9d31-e919c1da9898
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245180738 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.pwrmgr_intr_test.4245180738
Directory /workspace/30.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.pwrmgr_intr_test.886111645
Short name T646
Test name
Test status
Simulation time 56697645 ps
CPU time 0.62 seconds
Started Aug 06 07:03:59 PM PDT 24
Finished Aug 06 07:04:00 PM PDT 24
Peak memory 195120 kb
Host smart-81fec939-e7cf-4e71-9a1f-174091e0b4a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886111645 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.pwrmgr_intr_test.886111645
Directory /workspace/31.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.pwrmgr_intr_test.712400397
Short name T77
Test name
Test status
Simulation time 48799856 ps
CPU time 0.61 seconds
Started Aug 06 07:04:04 PM PDT 24
Finished Aug 06 07:04:05 PM PDT 24
Peak memory 195280 kb
Host smart-227d80bb-b6d1-492a-876d-f597a8fdd44e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712400397 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.pwrmgr_intr_test.712400397
Directory /workspace/32.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.pwrmgr_intr_test.4135573046
Short name T641
Test name
Test status
Simulation time 55015763 ps
CPU time 0.66 seconds
Started Aug 06 07:03:59 PM PDT 24
Finished Aug 06 07:04:00 PM PDT 24
Peak memory 195124 kb
Host smart-8ff27c71-ccfd-4065-822d-7ba435d62198
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135573046 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.pwrmgr_intr_test.4135573046
Directory /workspace/33.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.pwrmgr_intr_test.2323313948
Short name T722
Test name
Test status
Simulation time 16771580 ps
CPU time 0.64 seconds
Started Aug 06 07:03:59 PM PDT 24
Finished Aug 06 07:04:00 PM PDT 24
Peak memory 195116 kb
Host smart-481a825d-eb8b-49b9-92e1-941e3ca2f051
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323313948 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.pwrmgr_intr_test.2323313948
Directory /workspace/34.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.pwrmgr_intr_test.1105938177
Short name T664
Test name
Test status
Simulation time 45164175 ps
CPU time 0.6 seconds
Started Aug 06 07:04:08 PM PDT 24
Finished Aug 06 07:04:09 PM PDT 24
Peak memory 195072 kb
Host smart-11709458-82c0-4df1-b8e2-5d750a2c4bcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105938177 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.pwrmgr_intr_test.1105938177
Directory /workspace/35.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.pwrmgr_intr_test.3084139988
Short name T653
Test name
Test status
Simulation time 61395141 ps
CPU time 0.64 seconds
Started Aug 06 07:03:59 PM PDT 24
Finished Aug 06 07:04:00 PM PDT 24
Peak memory 195120 kb
Host smart-9b2d6d06-c18e-484a-bfd3-19685507d81c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084139988 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.pwrmgr_intr_test.3084139988
Directory /workspace/36.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.pwrmgr_intr_test.40998122
Short name T649
Test name
Test status
Simulation time 18408352 ps
CPU time 0.61 seconds
Started Aug 06 07:04:00 PM PDT 24
Finished Aug 06 07:04:00 PM PDT 24
Peak memory 195024 kb
Host smart-4091649c-8042-47ab-b527-186d59522a9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40998122 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.pwrmgr_intr_test.40998122
Directory /workspace/37.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.pwrmgr_intr_test.119604147
Short name T729
Test name
Test status
Simulation time 18177252 ps
CPU time 0.59 seconds
Started Aug 06 07:04:00 PM PDT 24
Finished Aug 06 07:04:00 PM PDT 24
Peak memory 195040 kb
Host smart-e63d197e-9600-448f-9539-894fb86ac18f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119604147 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.pwrmgr_intr_test.119604147
Directory /workspace/38.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.pwrmgr_intr_test.2280927079
Short name T710
Test name
Test status
Simulation time 32579321 ps
CPU time 0.59 seconds
Started Aug 06 07:03:59 PM PDT 24
Finished Aug 06 07:03:59 PM PDT 24
Peak memory 195120 kb
Host smart-c51a799c-1ae2-4e6f-9f40-afda9815554a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280927079 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.pwrmgr_intr_test.2280927079
Directory /workspace/39.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.1304444806
Short name T164
Test name
Test status
Simulation time 29735469 ps
CPU time 0.77 seconds
Started Aug 06 07:03:42 PM PDT 24
Finished Aug 06 07:03:43 PM PDT 24
Peak memory 195088 kb
Host smart-99e756c6-9e20-47fd-837b-4f2b9f43eebb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304444806 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_aliasing.1
304444806
Directory /workspace/4.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.2092037741
Short name T733
Test name
Test status
Simulation time 380932388 ps
CPU time 1.89 seconds
Started Aug 06 07:03:42 PM PDT 24
Finished Aug 06 07:03:44 PM PDT 24
Peak memory 195276 kb
Host smart-57703c7c-097c-4c5c-bf40-ce165165672c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092037741 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_bit_bash.2
092037741
Directory /workspace/4.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.4225609606
Short name T718
Test name
Test status
Simulation time 59178196 ps
CPU time 0.65 seconds
Started Aug 06 07:03:42 PM PDT 24
Finished Aug 06 07:03:43 PM PDT 24
Peak memory 196316 kb
Host smart-de534a11-39f0-4456-8944-38b8a18faf38
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225609606 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_hw_reset.4
225609606
Directory /workspace/4.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.1881639700
Short name T685
Test name
Test status
Simulation time 278378591 ps
CPU time 0.88 seconds
Started Aug 06 07:03:42 PM PDT 24
Finished Aug 06 07:03:43 PM PDT 24
Peak memory 195356 kb
Host smart-b7bfe295-2b74-42fc-8c8b-4457e993bf7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881639700 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.pwrmgr_csr_mem_rw_with_rand_reset.1881639700
Directory /workspace/4.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_rw.4074574018
Short name T109
Test name
Test status
Simulation time 79654918 ps
CPU time 0.61 seconds
Started Aug 06 07:03:48 PM PDT 24
Finished Aug 06 07:03:49 PM PDT 24
Peak memory 197304 kb
Host smart-f19befe0-dc62-44b4-92bc-bfec53804330
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074574018 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_rw.4074574018
Directory /workspace/4.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_intr_test.4043063776
Short name T645
Test name
Test status
Simulation time 67796815 ps
CPU time 0.59 seconds
Started Aug 06 07:03:45 PM PDT 24
Finished Aug 06 07:03:46 PM PDT 24
Peak memory 195104 kb
Host smart-f80489ff-bcf5-4a94-9cfb-1db29f0cac8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043063776 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_intr_test.4043063776
Directory /workspace/4.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.1588729946
Short name T735
Test name
Test status
Simulation time 162332593 ps
CPU time 0.91 seconds
Started Aug 06 07:03:42 PM PDT 24
Finished Aug 06 07:03:43 PM PDT 24
Peak memory 198452 kb
Host smart-02600a8d-8b2d-4c0a-9a54-00c44c76620d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588729946 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sa
me_csr_outstanding.1588729946
Directory /workspace/4.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_tl_errors.3425379429
Short name T682
Test name
Test status
Simulation time 86538995 ps
CPU time 2.19 seconds
Started Aug 06 07:03:44 PM PDT 24
Finished Aug 06 07:03:47 PM PDT 24
Peak memory 196484 kb
Host smart-6f37c1f6-e942-48d9-a02e-b9e41f994249
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425379429 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_errors.3425379429
Directory /workspace/4.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.2592898700
Short name T83
Test name
Test status
Simulation time 598962128 ps
CPU time 1.46 seconds
Started Aug 06 07:03:44 PM PDT 24
Finished Aug 06 07:03:46 PM PDT 24
Peak memory 200632 kb
Host smart-33a0c602-5fff-403b-a91d-b4a11e361fa5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592898700 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_intg_err
.2592898700
Directory /workspace/4.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.pwrmgr_intr_test.180681256
Short name T684
Test name
Test status
Simulation time 45599383 ps
CPU time 0.6 seconds
Started Aug 06 07:03:55 PM PDT 24
Finished Aug 06 07:03:55 PM PDT 24
Peak memory 195060 kb
Host smart-822fe815-819d-4c59-99b3-94b2379600a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180681256 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.pwrmgr_intr_test.180681256
Directory /workspace/40.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.pwrmgr_intr_test.2998907226
Short name T693
Test name
Test status
Simulation time 19547800 ps
CPU time 0.64 seconds
Started Aug 06 07:03:51 PM PDT 24
Finished Aug 06 07:03:52 PM PDT 24
Peak memory 195044 kb
Host smart-511bacac-6627-4655-9a8c-0d51af81c279
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998907226 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.pwrmgr_intr_test.2998907226
Directory /workspace/41.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.pwrmgr_intr_test.1244762322
Short name T721
Test name
Test status
Simulation time 30434405 ps
CPU time 0.58 seconds
Started Aug 06 07:03:53 PM PDT 24
Finished Aug 06 07:03:54 PM PDT 24
Peak memory 195048 kb
Host smart-63a9d3dd-ca63-47ea-8c0c-5795e95fb06a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244762322 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.pwrmgr_intr_test.1244762322
Directory /workspace/42.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.pwrmgr_intr_test.4082168939
Short name T162
Test name
Test status
Simulation time 19124499 ps
CPU time 0.61 seconds
Started Aug 06 07:03:52 PM PDT 24
Finished Aug 06 07:03:52 PM PDT 24
Peak memory 195040 kb
Host smart-6da8f22e-6f5f-4ae0-b61b-27dce3440457
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082168939 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.pwrmgr_intr_test.4082168939
Directory /workspace/43.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.pwrmgr_intr_test.1310762471
Short name T731
Test name
Test status
Simulation time 40823746 ps
CPU time 0.61 seconds
Started Aug 06 07:03:49 PM PDT 24
Finished Aug 06 07:03:50 PM PDT 24
Peak memory 194928 kb
Host smart-a71d187a-e85a-44e1-93a3-56fd6e1a1307
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310762471 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.pwrmgr_intr_test.1310762471
Directory /workspace/44.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.pwrmgr_intr_test.1515292118
Short name T674
Test name
Test status
Simulation time 18297592 ps
CPU time 0.59 seconds
Started Aug 06 07:04:09 PM PDT 24
Finished Aug 06 07:04:10 PM PDT 24
Peak memory 195076 kb
Host smart-7bfae85d-de72-4c91-bb9f-bf56bc3313a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515292118 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.pwrmgr_intr_test.1515292118
Directory /workspace/45.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.pwrmgr_intr_test.3859856442
Short name T632
Test name
Test status
Simulation time 93728538 ps
CPU time 0.56 seconds
Started Aug 06 07:04:06 PM PDT 24
Finished Aug 06 07:04:07 PM PDT 24
Peak memory 195056 kb
Host smart-ad9c28ca-cc1a-4e0e-b9f0-e57f31b7c3c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859856442 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.pwrmgr_intr_test.3859856442
Directory /workspace/46.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.pwrmgr_intr_test.2855785863
Short name T644
Test name
Test status
Simulation time 20889943 ps
CPU time 0.62 seconds
Started Aug 06 07:04:06 PM PDT 24
Finished Aug 06 07:04:07 PM PDT 24
Peak memory 195076 kb
Host smart-96b68d73-017c-4c45-a0a3-dc631b7064ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855785863 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.pwrmgr_intr_test.2855785863
Directory /workspace/47.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.pwrmgr_intr_test.333815664
Short name T676
Test name
Test status
Simulation time 46259873 ps
CPU time 0.59 seconds
Started Aug 06 07:04:06 PM PDT 24
Finished Aug 06 07:04:06 PM PDT 24
Peak memory 195084 kb
Host smart-2d995ba6-6858-4dcf-b24e-05b56b3a2e4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333815664 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.pwrmgr_intr_test.333815664
Directory /workspace/48.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.pwrmgr_intr_test.3999311456
Short name T630
Test name
Test status
Simulation time 26656606 ps
CPU time 0.6 seconds
Started Aug 06 07:04:10 PM PDT 24
Finished Aug 06 07:04:11 PM PDT 24
Peak memory 195064 kb
Host smart-a0f90fa4-a114-4cfc-a795-1028e228533d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999311456 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.pwrmgr_intr_test.3999311456
Directory /workspace/49.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.2523639722
Short name T657
Test name
Test status
Simulation time 46119738 ps
CPU time 0.8 seconds
Started Aug 06 07:03:42 PM PDT 24
Finished Aug 06 07:03:43 PM PDT 24
Peak memory 200560 kb
Host smart-c0092b48-0cd4-451d-ad33-0699d6549848
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523639722 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.pwrmgr_csr_mem_rw_with_rand_reset.2523639722
Directory /workspace/5.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_csr_rw.3584185999
Short name T634
Test name
Test status
Simulation time 48438883 ps
CPU time 0.62 seconds
Started Aug 06 07:03:42 PM PDT 24
Finished Aug 06 07:03:43 PM PDT 24
Peak memory 197248 kb
Host smart-bfd9d041-9f1e-4402-9cfc-272f2ce2a507
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584185999 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_csr_rw.3584185999
Directory /workspace/5.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_intr_test.2428265733
Short name T716
Test name
Test status
Simulation time 17136985 ps
CPU time 0.61 seconds
Started Aug 06 07:03:48 PM PDT 24
Finished Aug 06 07:03:48 PM PDT 24
Peak memory 195020 kb
Host smart-9aa3ce58-eb05-4fe5-930c-45eda7de5547
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428265733 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_intr_test.2428265733
Directory /workspace/5.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.1451104051
Short name T691
Test name
Test status
Simulation time 41539535 ps
CPU time 0.86 seconds
Started Aug 06 07:03:39 PM PDT 24
Finished Aug 06 07:03:40 PM PDT 24
Peak memory 195124 kb
Host smart-ee36b60d-5070-44eb-a33a-7abcfef0b1e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451104051 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sa
me_csr_outstanding.1451104051
Directory /workspace/5.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_tl_errors.2521954050
Short name T669
Test name
Test status
Simulation time 36730543 ps
CPU time 1.57 seconds
Started Aug 06 07:03:43 PM PDT 24
Finished Aug 06 07:03:45 PM PDT 24
Peak memory 196352 kb
Host smart-0105c858-f17a-42ce-aa5c-b87a84c80cc4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521954050 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_errors.2521954050
Directory /workspace/5.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.2054539268
Short name T61
Test name
Test status
Simulation time 106854103 ps
CPU time 1.17 seconds
Started Aug 06 07:03:50 PM PDT 24
Finished Aug 06 07:03:52 PM PDT 24
Peak memory 200476 kb
Host smart-08bf0f03-9ec4-4da8-85a2-cacee459a1cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054539268 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_intg_err
.2054539268
Directory /workspace/5.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.703579023
Short name T701
Test name
Test status
Simulation time 58014083 ps
CPU time 1.2 seconds
Started Aug 06 07:03:42 PM PDT 24
Finished Aug 06 07:03:43 PM PDT 24
Peak memory 200776 kb
Host smart-e322f37c-3a1a-4381-a731-2a91590afc00
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703579023 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.pwrmgr_csr_mem_rw_with_rand_reset.703579023
Directory /workspace/6.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_csr_rw.558392088
Short name T163
Test name
Test status
Simulation time 23285368 ps
CPU time 0.67 seconds
Started Aug 06 07:03:43 PM PDT 24
Finished Aug 06 07:03:43 PM PDT 24
Peak memory 197292 kb
Host smart-efba73e9-4d85-40f3-b506-06b80967e658
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558392088 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_csr_rw.558392088
Directory /workspace/6.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_intr_test.4090181478
Short name T635
Test name
Test status
Simulation time 33074601 ps
CPU time 0.66 seconds
Started Aug 06 07:03:43 PM PDT 24
Finished Aug 06 07:03:44 PM PDT 24
Peak memory 195068 kb
Host smart-f72b7f86-d4c1-4bad-b5f4-774169948b15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090181478 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_intr_test.4090181478
Directory /workspace/6.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.1111600268
Short name T119
Test name
Test status
Simulation time 37091022 ps
CPU time 0.71 seconds
Started Aug 06 07:03:43 PM PDT 24
Finished Aug 06 07:03:44 PM PDT 24
Peak memory 197392 kb
Host smart-9d17afb4-17b1-405a-97ad-d25a57834981
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111600268 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sa
me_csr_outstanding.1111600268
Directory /workspace/6.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_tl_errors.288349316
Short name T690
Test name
Test status
Simulation time 124558257 ps
CPU time 1.17 seconds
Started Aug 06 07:03:40 PM PDT 24
Finished Aug 06 07:03:41 PM PDT 24
Peak memory 195532 kb
Host smart-8647916c-bceb-4c1b-b980-29dae6c86031
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288349316 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_errors.288349316
Directory /workspace/6.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.1032124235
Short name T82
Test name
Test status
Simulation time 253458405 ps
CPU time 1.12 seconds
Started Aug 06 07:03:42 PM PDT 24
Finished Aug 06 07:03:43 PM PDT 24
Peak memory 200448 kb
Host smart-62779530-7fd9-409e-bdb5-0a79803628cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032124235 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_intg_err
.1032124235
Directory /workspace/6.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.3827805437
Short name T651
Test name
Test status
Simulation time 60055572 ps
CPU time 1.24 seconds
Started Aug 06 07:03:38 PM PDT 24
Finished Aug 06 07:03:39 PM PDT 24
Peak memory 196400 kb
Host smart-c89752c7-4d5b-43c8-a32e-47e68090f799
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827805437 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.pwrmgr_csr_mem_rw_with_rand_reset.3827805437
Directory /workspace/7.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_csr_rw.449369280
Short name T117
Test name
Test status
Simulation time 34619629 ps
CPU time 0.7 seconds
Started Aug 06 07:03:42 PM PDT 24
Finished Aug 06 07:03:43 PM PDT 24
Peak memory 197328 kb
Host smart-560903a1-ac56-41af-983d-e68bdc5d59e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449369280 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_csr_rw.449369280
Directory /workspace/7.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_intr_test.428439918
Short name T713
Test name
Test status
Simulation time 53540892 ps
CPU time 0.62 seconds
Started Aug 06 07:03:38 PM PDT 24
Finished Aug 06 07:03:39 PM PDT 24
Peak memory 194972 kb
Host smart-02d2e449-8718-4292-8d7c-1a71ebe1394d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428439918 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_intr_test.428439918
Directory /workspace/7.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.3512889381
Short name T667
Test name
Test status
Simulation time 28631361 ps
CPU time 0.74 seconds
Started Aug 06 07:03:38 PM PDT 24
Finished Aug 06 07:03:39 PM PDT 24
Peak memory 197352 kb
Host smart-0e9cbd4f-aabe-4557-8956-68f7396b33bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512889381 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sa
me_csr_outstanding.3512889381
Directory /workspace/7.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_tl_errors.1202410177
Short name T698
Test name
Test status
Simulation time 180116393 ps
CPU time 1.25 seconds
Started Aug 06 07:03:38 PM PDT 24
Finished Aug 06 07:03:39 PM PDT 24
Peak memory 196380 kb
Host smart-e8b54756-a424-4abb-9e5c-f9f2daabb172
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202410177 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_errors.1202410177
Directory /workspace/7.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.600808759
Short name T150
Test name
Test status
Simulation time 192635538 ps
CPU time 1.59 seconds
Started Aug 06 07:03:41 PM PDT 24
Finished Aug 06 07:03:42 PM PDT 24
Peak memory 195208 kb
Host smart-d54af404-eb92-490c-9bab-2a32bbc74454
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600808759 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_intg_err.
600808759
Directory /workspace/7.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.682890292
Short name T652
Test name
Test status
Simulation time 84100244 ps
CPU time 1.18 seconds
Started Aug 06 07:03:37 PM PDT 24
Finished Aug 06 07:03:38 PM PDT 24
Peak memory 196604 kb
Host smart-ba9088d6-24d0-46f6-9471-d1ab47f6a943
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682890292 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.pwrmgr_csr_mem_rw_with_rand_reset.682890292
Directory /workspace/8.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_csr_rw.3653624840
Short name T666
Test name
Test status
Simulation time 44540487 ps
CPU time 0.63 seconds
Started Aug 06 07:03:39 PM PDT 24
Finished Aug 06 07:03:40 PM PDT 24
Peak memory 195124 kb
Host smart-a458b269-8ab0-41bb-a253-55b87cb31a8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653624840 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_csr_rw.3653624840
Directory /workspace/8.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_intr_test.532336024
Short name T696
Test name
Test status
Simulation time 46874843 ps
CPU time 0.62 seconds
Started Aug 06 07:03:38 PM PDT 24
Finished Aug 06 07:03:39 PM PDT 24
Peak memory 195064 kb
Host smart-f1337239-6fed-45c2-af86-92f9158fc12d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532336024 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_intr_test.532336024
Directory /workspace/8.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.489491285
Short name T121
Test name
Test status
Simulation time 47264434 ps
CPU time 0.93 seconds
Started Aug 06 07:03:41 PM PDT 24
Finished Aug 06 07:03:42 PM PDT 24
Peak memory 198488 kb
Host smart-c165ab68-b580-47e7-85a1-e50828986fde
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489491285 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sam
e_csr_outstanding.489491285
Directory /workspace/8.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_tl_errors.650404540
Short name T23
Test name
Test status
Simulation time 471356793 ps
CPU time 1.87 seconds
Started Aug 06 07:03:41 PM PDT 24
Finished Aug 06 07:03:43 PM PDT 24
Peak memory 197432 kb
Host smart-b1fcf6d8-cfae-41d2-af4e-805497281de2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650404540 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_errors.650404540
Directory /workspace/8.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.1452225998
Short name T694
Test name
Test status
Simulation time 104436959 ps
CPU time 1.12 seconds
Started Aug 06 07:03:39 PM PDT 24
Finished Aug 06 07:03:40 PM PDT 24
Peak memory 200400 kb
Host smart-92b9c93f-517c-4439-b69a-ada5a864cdca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452225998 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_intg_err
.1452225998
Directory /workspace/8.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.942629493
Short name T736
Test name
Test status
Simulation time 42364477 ps
CPU time 0.8 seconds
Started Aug 06 07:03:39 PM PDT 24
Finished Aug 06 07:03:40 PM PDT 24
Peak memory 195256 kb
Host smart-07a7443d-690f-4980-9b82-8af78672ebae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942629493 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.pwrmgr_csr_mem_rw_with_rand_reset.942629493
Directory /workspace/9.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_csr_rw.2587741958
Short name T697
Test name
Test status
Simulation time 52304139 ps
CPU time 0.64 seconds
Started Aug 06 07:03:38 PM PDT 24
Finished Aug 06 07:03:39 PM PDT 24
Peak memory 197312 kb
Host smart-0cc94c52-01b4-4165-adb5-45cb8b8072db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587741958 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_csr_rw.2587741958
Directory /workspace/9.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_intr_test.4136724005
Short name T707
Test name
Test status
Simulation time 189807919 ps
CPU time 0.6 seconds
Started Aug 06 07:03:40 PM PDT 24
Finished Aug 06 07:03:41 PM PDT 24
Peak memory 195064 kb
Host smart-3a2d3d9f-9e33-4eca-90ac-363d35b9407f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136724005 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_intr_test.4136724005
Directory /workspace/9.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.989276869
Short name T80
Test name
Test status
Simulation time 72194865 ps
CPU time 0.76 seconds
Started Aug 06 07:03:44 PM PDT 24
Finished Aug 06 07:03:45 PM PDT 24
Peak memory 197452 kb
Host smart-0ca736d9-fd64-4c18-9279-8cc5971eeece
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989276869 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sam
e_csr_outstanding.989276869
Directory /workspace/9.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_tl_errors.1949569695
Short name T714
Test name
Test status
Simulation time 305956784 ps
CPU time 1.81 seconds
Started Aug 06 07:03:43 PM PDT 24
Finished Aug 06 07:03:45 PM PDT 24
Peak memory 196368 kb
Host smart-68f1520b-9195-4703-90f1-43a93ae7b529
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949569695 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_errors.1949569695
Directory /workspace/9.pwrmgr_tl_errors/latest

Test location /workspace/coverage/default/0.pwrmgr_aborted_low_power.4029905243
Short name T296
Test name
Test status
Simulation time 49303236 ps
CPU time 0.66 seconds
Started Aug 06 07:48:34 PM PDT 24
Finished Aug 06 07:48:35 PM PDT 24
Peak memory 198664 kb
Host smart-79aa6275-eeed-473d-bcc4-003362e3bf6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029905243 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_aborted_low_power.4029905243
Directory /workspace/0.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/0.pwrmgr_disable_rom_integrity_check.20675657
Short name T138
Test name
Test status
Simulation time 68736629 ps
CPU time 0.67 seconds
Started Aug 06 07:48:40 PM PDT 24
Finished Aug 06 07:48:41 PM PDT 24
Peak memory 198288 kb
Host smart-f3e32407-7dd2-4c28-b5b0-98dcc253f678
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20675657 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_int
egrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_disabl
e_rom_integrity_check.20675657
Directory /workspace/0.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/0.pwrmgr_esc_clk_rst_malfunc.2708084825
Short name T300
Test name
Test status
Simulation time 32213085 ps
CPU time 0.62 seconds
Started Aug 06 07:48:43 PM PDT 24
Finished Aug 06 07:48:44 PM PDT 24
Peak memory 197296 kb
Host smart-f86ae968-d3b1-4ef8-8242-7ee7ab1de959
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708084825 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_esc_clk_rst_
malfunc.2708084825
Directory /workspace/0.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/0.pwrmgr_escalation_timeout.2720085208
Short name T238
Test name
Test status
Simulation time 636330876 ps
CPU time 0.96 seconds
Started Aug 06 07:48:41 PM PDT 24
Finished Aug 06 07:48:42 PM PDT 24
Peak memory 198116 kb
Host smart-a4d2f115-8e0a-4c19-b4b8-56986dbc49fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720085208 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_escalation_timeout.2720085208
Directory /workspace/0.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/0.pwrmgr_glitch.611905673
Short name T322
Test name
Test status
Simulation time 58407424 ps
CPU time 0.64 seconds
Started Aug 06 07:48:44 PM PDT 24
Finished Aug 06 07:48:44 PM PDT 24
Peak memory 197388 kb
Host smart-92aeeab3-5897-4a7e-8dad-52562d283f0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611905673 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_glitch.611905673
Directory /workspace/0.pwrmgr_glitch/latest

Test location /workspace/coverage/default/0.pwrmgr_global_esc.1086391051
Short name T607
Test name
Test status
Simulation time 361984925 ps
CPU time 0.62 seconds
Started Aug 06 07:48:43 PM PDT 24
Finished Aug 06 07:48:43 PM PDT 24
Peak memory 198076 kb
Host smart-27db64e0-7f93-4a30-8f49-2a748a001150
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086391051 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_global_esc.1086391051
Directory /workspace/0.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/0.pwrmgr_lowpower_invalid.3878336959
Short name T173
Test name
Test status
Simulation time 129619211 ps
CPU time 0.69 seconds
Started Aug 06 07:48:45 PM PDT 24
Finished Aug 06 07:48:46 PM PDT 24
Peak memory 201376 kb
Host smart-5ec89550-36a0-42b1-8d00-1b86e14dab23
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878336959 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_lowpower_invali
d.3878336959
Directory /workspace/0.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/0.pwrmgr_reset.1952835375
Short name T569
Test name
Test status
Simulation time 28647778 ps
CPU time 0.69 seconds
Started Aug 06 07:48:47 PM PDT 24
Finished Aug 06 07:48:48 PM PDT 24
Peak memory 199204 kb
Host smart-d4444124-0333-4427-b620-c52f458a13f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952835375 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset.1952835375
Directory /workspace/0.pwrmgr_reset/latest

Test location /workspace/coverage/default/0.pwrmgr_reset_invalid.3745679456
Short name T573
Test name
Test status
Simulation time 246313024 ps
CPU time 0.8 seconds
Started Aug 06 07:48:31 PM PDT 24
Finished Aug 06 07:48:32 PM PDT 24
Peak memory 209540 kb
Host smart-33fa0914-01bf-4bc6-8849-4a495e30becd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745679456 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset_invalid.3745679456
Directory /workspace/0.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm.3987658798
Short name T19
Test name
Test status
Simulation time 1202470657 ps
CPU time 1.45 seconds
Started Aug 06 07:48:40 PM PDT 24
Finished Aug 06 07:48:42 PM PDT 24
Peak memory 218040 kb
Host smart-b0e40be0-48fa-481a-afa3-1c90da23d08c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987658798 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm.3987658798
Directory /workspace/0.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm_rstmgr_intersig_mubi.2808264932
Short name T297
Test name
Test status
Simulation time 49092615 ps
CPU time 0.85 seconds
Started Aug 06 07:48:34 PM PDT 24
Finished Aug 06 07:48:35 PM PDT 24
Peak memory 199340 kb
Host smart-f758acfb-ddab-4666-b4ab-bd2cb462f29c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808264932 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2808264932
Directory /workspace/0.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/0.pwrmgr_smoke.3115741041
Short name T91
Test name
Test status
Simulation time 31685217 ps
CPU time 0.67 seconds
Started Aug 06 07:48:35 PM PDT 24
Finished Aug 06 07:48:36 PM PDT 24
Peak memory 198504 kb
Host smart-726d6fc8-e2b4-4301-8c46-6d053a402566
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115741041 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_smoke.3115741041
Directory /workspace/0.pwrmgr_smoke/latest

Test location /workspace/coverage/default/1.pwrmgr_aborted_low_power.626377938
Short name T384
Test name
Test status
Simulation time 105927579 ps
CPU time 0.81 seconds
Started Aug 06 07:48:43 PM PDT 24
Finished Aug 06 07:48:44 PM PDT 24
Peak memory 198792 kb
Host smart-2631f312-c7f0-464b-a667-b207371552f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626377938 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_aborted_low_power.626377938
Directory /workspace/1.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/1.pwrmgr_esc_clk_rst_malfunc.3599303689
Short name T561
Test name
Test status
Simulation time 28958406 ps
CPU time 0.62 seconds
Started Aug 06 07:48:41 PM PDT 24
Finished Aug 06 07:48:42 PM PDT 24
Peak memory 198032 kb
Host smart-a8175510-5ac3-4d56-b24b-7dd37509eadf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599303689 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_esc_clk_rst_
malfunc.3599303689
Directory /workspace/1.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/1.pwrmgr_escalation_timeout.4290468321
Short name T256
Test name
Test status
Simulation time 161653672 ps
CPU time 0.98 seconds
Started Aug 06 07:48:37 PM PDT 24
Finished Aug 06 07:48:38 PM PDT 24
Peak memory 198084 kb
Host smart-81e07538-8b55-4e99-bb2d-54ce15b20e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290468321 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_escalation_timeout.4290468321
Directory /workspace/1.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/1.pwrmgr_glitch.171554102
Short name T301
Test name
Test status
Simulation time 65232836 ps
CPU time 0.62 seconds
Started Aug 06 07:48:43 PM PDT 24
Finished Aug 06 07:48:44 PM PDT 24
Peak memory 198084 kb
Host smart-8de26f21-8f70-4e0f-a468-55ecc0984449
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171554102 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_glitch.171554102
Directory /workspace/1.pwrmgr_glitch/latest

Test location /workspace/coverage/default/1.pwrmgr_global_esc.2890778399
Short name T615
Test name
Test status
Simulation time 95310768 ps
CPU time 0.6 seconds
Started Aug 06 07:48:47 PM PDT 24
Finished Aug 06 07:48:48 PM PDT 24
Peak memory 198188 kb
Host smart-6485e397-41a2-4ba0-9303-ee4ec688dbe9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890778399 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_global_esc.2890778399
Directory /workspace/1.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/1.pwrmgr_lowpower_invalid.1411760451
Short name T92
Test name
Test status
Simulation time 54456358 ps
CPU time 0.7 seconds
Started Aug 06 07:48:47 PM PDT 24
Finished Aug 06 07:48:48 PM PDT 24
Peak memory 201528 kb
Host smart-cc76e869-7715-4c90-bde0-f45140b32d2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411760451 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_lowpower_invali
d.1411760451
Directory /workspace/1.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/1.pwrmgr_reset.544900585
Short name T426
Test name
Test status
Simulation time 99748851 ps
CPU time 0.76 seconds
Started Aug 06 07:48:33 PM PDT 24
Finished Aug 06 07:48:34 PM PDT 24
Peak memory 198692 kb
Host smart-942e8234-0d5e-473b-a157-38c006df50f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544900585 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset.544900585
Directory /workspace/1.pwrmgr_reset/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm.3325614946
Short name T18
Test name
Test status
Simulation time 478976356 ps
CPU time 1.08 seconds
Started Aug 06 07:48:40 PM PDT 24
Finished Aug 06 07:48:42 PM PDT 24
Peak memory 217824 kb
Host smart-dd63ca9a-0dd0-41db-94c2-60bc4431c3af
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325614946 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm.3325614946
Directory /workspace/1.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm_rstmgr_intersig_mubi.811348971
Short name T400
Test name
Test status
Simulation time 64768767 ps
CPU time 0.84 seconds
Started Aug 06 07:48:42 PM PDT 24
Finished Aug 06 07:48:43 PM PDT 24
Peak memory 199316 kb
Host smart-3c5efc5b-9484-42b9-8c14-63b9b45aa8a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811348971 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.811348971
Directory /workspace/1.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/1.pwrmgr_smoke.3033789519
Short name T252
Test name
Test status
Simulation time 52791762 ps
CPU time 0.63 seconds
Started Aug 06 07:48:36 PM PDT 24
Finished Aug 06 07:48:36 PM PDT 24
Peak memory 198536 kb
Host smart-eebda12e-2644-4ff1-a9fe-da1fd9c8db56
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033789519 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_smoke.3033789519
Directory /workspace/1.pwrmgr_smoke/latest

Test location /workspace/coverage/default/10.pwrmgr_aborted_low_power.2765862842
Short name T469
Test name
Test status
Simulation time 214139428 ps
CPU time 0.78 seconds
Started Aug 06 07:49:29 PM PDT 24
Finished Aug 06 07:49:29 PM PDT 24
Peak memory 200044 kb
Host smart-1fe75dd4-d039-4d8e-973e-851791a8d071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765862842 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_aborted_low_power.2765862842
Directory /workspace/10.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/10.pwrmgr_esc_clk_rst_malfunc.1297578299
Short name T595
Test name
Test status
Simulation time 30833723 ps
CPU time 0.62 seconds
Started Aug 06 07:49:30 PM PDT 24
Finished Aug 06 07:49:31 PM PDT 24
Peak memory 197312 kb
Host smart-70c88505-4378-46da-a361-9f07aa8c7d8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297578299 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_esc_clk_rst
_malfunc.1297578299
Directory /workspace/10.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/10.pwrmgr_escalation_timeout.3719762818
Short name T518
Test name
Test status
Simulation time 164210409 ps
CPU time 0.94 seconds
Started Aug 06 07:49:26 PM PDT 24
Finished Aug 06 07:49:27 PM PDT 24
Peak memory 198384 kb
Host smart-c9f58419-3e30-471d-8bc1-115aae17aa48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719762818 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_escalation_timeout.3719762818
Directory /workspace/10.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/10.pwrmgr_glitch.975102235
Short name T396
Test name
Test status
Simulation time 40272633 ps
CPU time 0.64 seconds
Started Aug 06 07:49:27 PM PDT 24
Finished Aug 06 07:49:28 PM PDT 24
Peak memory 198036 kb
Host smart-8cd161c4-6e69-436a-82d6-2d817fee4be0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975102235 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_glitch.975102235
Directory /workspace/10.pwrmgr_glitch/latest

Test location /workspace/coverage/default/10.pwrmgr_global_esc.2765170442
Short name T273
Test name
Test status
Simulation time 58950415 ps
CPU time 0.58 seconds
Started Aug 06 07:49:25 PM PDT 24
Finished Aug 06 07:49:25 PM PDT 24
Peak memory 198104 kb
Host smart-9cefcce4-d90c-4aa6-a5ad-06b013675062
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765170442 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_global_esc.2765170442
Directory /workspace/10.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/10.pwrmgr_reset.4282229937
Short name T265
Test name
Test status
Simulation time 228824726 ps
CPU time 0.69 seconds
Started Aug 06 07:49:28 PM PDT 24
Finished Aug 06 07:49:29 PM PDT 24
Peak memory 198352 kb
Host smart-46d94986-36fb-4524-b4ec-941cb90031a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282229937 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset.4282229937
Directory /workspace/10.pwrmgr_reset/latest

Test location /workspace/coverage/default/10.pwrmgr_reset_invalid.1862241690
Short name T348
Test name
Test status
Simulation time 180154799 ps
CPU time 0.83 seconds
Started Aug 06 07:49:26 PM PDT 24
Finished Aug 06 07:49:27 PM PDT 24
Peak memory 209476 kb
Host smart-25404f94-f11c-4fbb-85d6-79e6a547743e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862241690 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset_invalid.1862241690
Directory /workspace/10.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/10.pwrmgr_sec_cm_rstmgr_intersig_mubi.2115420321
Short name T253
Test name
Test status
Simulation time 127675333 ps
CPU time 0.85 seconds
Started Aug 06 07:49:30 PM PDT 24
Finished Aug 06 07:49:31 PM PDT 24
Peak memory 199376 kb
Host smart-d530ed81-bc4f-4dbe-8c04-5651d44be9ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115420321 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2115420321
Directory /workspace/10.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/10.pwrmgr_smoke.2714692019
Short name T380
Test name
Test status
Simulation time 34550955 ps
CPU time 0.63 seconds
Started Aug 06 07:49:26 PM PDT 24
Finished Aug 06 07:49:27 PM PDT 24
Peak memory 199400 kb
Host smart-25b626bb-5bb8-43e0-bec3-592c6936200e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714692019 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_smoke.2714692019
Directory /workspace/10.pwrmgr_smoke/latest

Test location /workspace/coverage/default/10.pwrmgr_wakeup.193597209
Short name T145
Test name
Test status
Simulation time 63713920 ps
CPU time 0.64 seconds
Started Aug 06 07:49:26 PM PDT 24
Finished Aug 06 07:49:27 PM PDT 24
Peak memory 198184 kb
Host smart-d79e92e2-0579-44d6-8e00-14d8c4c87ef7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193597209 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_wakeup.193597209
Directory /workspace/10.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/11.pwrmgr_aborted_low_power.1907646937
Short name T334
Test name
Test status
Simulation time 98499278 ps
CPU time 0.83 seconds
Started Aug 06 07:49:29 PM PDT 24
Finished Aug 06 07:49:30 PM PDT 24
Peak memory 200096 kb
Host smart-67e30940-b90e-4136-a789-9679fc12457f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907646937 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_aborted_low_power.1907646937
Directory /workspace/11.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/11.pwrmgr_esc_clk_rst_malfunc.1247901332
Short name T590
Test name
Test status
Simulation time 44993154 ps
CPU time 0.64 seconds
Started Aug 06 07:49:32 PM PDT 24
Finished Aug 06 07:49:32 PM PDT 24
Peak memory 197376 kb
Host smart-a5f89537-fb0d-4ffb-84b8-d73f67198b12
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247901332 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_esc_clk_rst
_malfunc.1247901332
Directory /workspace/11.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/11.pwrmgr_escalation_timeout.3013338087
Short name T524
Test name
Test status
Simulation time 286383226 ps
CPU time 1.01 seconds
Started Aug 06 07:49:27 PM PDT 24
Finished Aug 06 07:49:28 PM PDT 24
Peak memory 198076 kb
Host smart-5a29440f-9ab8-4c17-8699-01224219f6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013338087 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_escalation_timeout.3013338087
Directory /workspace/11.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/11.pwrmgr_glitch.1760058911
Short name T541
Test name
Test status
Simulation time 64201534 ps
CPU time 0.61 seconds
Started Aug 06 07:49:26 PM PDT 24
Finished Aug 06 07:49:27 PM PDT 24
Peak memory 198056 kb
Host smart-a6dd5564-1baa-4e49-8ad9-8121bc4e6429
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760058911 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_glitch.1760058911
Directory /workspace/11.pwrmgr_glitch/latest

Test location /workspace/coverage/default/11.pwrmgr_global_esc.1824175865
Short name T423
Test name
Test status
Simulation time 36157989 ps
CPU time 0.62 seconds
Started Aug 06 07:49:28 PM PDT 24
Finished Aug 06 07:49:29 PM PDT 24
Peak memory 198100 kb
Host smart-e791837b-4ad6-4f9b-8ee7-3ece3bd57c12
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824175865 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_global_esc.1824175865
Directory /workspace/11.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/11.pwrmgr_lowpower_invalid.3492598977
Short name T441
Test name
Test status
Simulation time 57231282 ps
CPU time 0.72 seconds
Started Aug 06 07:49:32 PM PDT 24
Finished Aug 06 07:49:32 PM PDT 24
Peak memory 201448 kb
Host smart-b7652f23-e541-485a-b672-19d2aa5eb17b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492598977 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_lowpower_inval
id.3492598977
Directory /workspace/11.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/11.pwrmgr_reset.444989342
Short name T552
Test name
Test status
Simulation time 25505114 ps
CPU time 0.7 seconds
Started Aug 06 07:49:25 PM PDT 24
Finished Aug 06 07:49:26 PM PDT 24
Peak memory 199180 kb
Host smart-0ae870c7-a96d-456e-82d6-ce729dd8b775
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444989342 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset.444989342
Directory /workspace/11.pwrmgr_reset/latest

Test location /workspace/coverage/default/11.pwrmgr_reset_invalid.926666787
Short name T320
Test name
Test status
Simulation time 200032988 ps
CPU time 0.8 seconds
Started Aug 06 07:49:26 PM PDT 24
Finished Aug 06 07:49:27 PM PDT 24
Peak memory 209484 kb
Host smart-40a8b029-a8f5-435d-b664-1a04fc6b9776
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926666787 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset_invalid.926666787
Directory /workspace/11.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/11.pwrmgr_sec_cm_ctrl_config_regwen.558357931
Short name T147
Test name
Test status
Simulation time 112857628 ps
CPU time 0.65 seconds
Started Aug 06 07:49:26 PM PDT 24
Finished Aug 06 07:49:27 PM PDT 24
Peak memory 198572 kb
Host smart-9a7b0ed4-5e49-4229-80e1-e772a6a629b3
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558357931 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_c
m_ctrl_config_regwen.558357931
Directory /workspace/11.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/11.pwrmgr_sec_cm_rstmgr_intersig_mubi.3034884404
Short name T444
Test name
Test status
Simulation time 67431831 ps
CPU time 0.8 seconds
Started Aug 06 07:49:31 PM PDT 24
Finished Aug 06 07:49:32 PM PDT 24
Peak memory 199048 kb
Host smart-ec0cac50-99b3-436a-821b-6b1691181a8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034884404 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3034884404
Directory /workspace/11.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/11.pwrmgr_smoke.645613695
Short name T459
Test name
Test status
Simulation time 51960594 ps
CPU time 0.7 seconds
Started Aug 06 07:49:28 PM PDT 24
Finished Aug 06 07:49:29 PM PDT 24
Peak memory 198504 kb
Host smart-14d99467-7ffd-486e-ab68-fceda88a8cff
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645613695 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_smoke.645613695
Directory /workspace/11.pwrmgr_smoke/latest

Test location /workspace/coverage/default/12.pwrmgr_aborted_low_power.1608544968
Short name T261
Test name
Test status
Simulation time 27877500 ps
CPU time 0.96 seconds
Started Aug 06 07:49:29 PM PDT 24
Finished Aug 06 07:49:30 PM PDT 24
Peak memory 200756 kb
Host smart-bee01cb5-4478-478f-94c3-08cc2d08b44a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608544968 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_aborted_low_power.1608544968
Directory /workspace/12.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/12.pwrmgr_esc_clk_rst_malfunc.94687942
Short name T346
Test name
Test status
Simulation time 31567112 ps
CPU time 0.61 seconds
Started Aug 06 07:49:29 PM PDT 24
Finished Aug 06 07:49:29 PM PDT 24
Peak memory 197332 kb
Host smart-b5095bab-21e0-4624-8680-fb6da4c05f41
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94687942 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_mal
func_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_esc_clk_rst_m
alfunc.94687942
Directory /workspace/12.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/12.pwrmgr_escalation_timeout.2214424452
Short name T228
Test name
Test status
Simulation time 597678153 ps
CPU time 0.93 seconds
Started Aug 06 07:49:39 PM PDT 24
Finished Aug 06 07:49:40 PM PDT 24
Peak memory 198104 kb
Host smart-9609095f-753d-4666-868a-31af8930a860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214424452 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_escalation_timeout.2214424452
Directory /workspace/12.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/12.pwrmgr_glitch.880611365
Short name T287
Test name
Test status
Simulation time 51677877 ps
CPU time 0.68 seconds
Started Aug 06 07:49:46 PM PDT 24
Finished Aug 06 07:49:47 PM PDT 24
Peak memory 198064 kb
Host smart-5f2745ab-55fb-41a7-b8a5-8be3baeed9df
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880611365 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_glitch.880611365
Directory /workspace/12.pwrmgr_glitch/latest

Test location /workspace/coverage/default/12.pwrmgr_global_esc.3661190007
Short name T443
Test name
Test status
Simulation time 45739234 ps
CPU time 0.64 seconds
Started Aug 06 07:49:39 PM PDT 24
Finished Aug 06 07:49:40 PM PDT 24
Peak memory 198096 kb
Host smart-ad386b77-80e6-4f1c-b5c4-fb5eb3037a7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661190007 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_global_esc.3661190007
Directory /workspace/12.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/12.pwrmgr_lowpower_invalid.2571452619
Short name T52
Test name
Test status
Simulation time 82066406 ps
CPU time 0.67 seconds
Started Aug 06 07:49:41 PM PDT 24
Finished Aug 06 07:49:42 PM PDT 24
Peak memory 201392 kb
Host smart-653b697e-32a2-4fe7-ae08-8b2d360d7299
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571452619 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_lowpower_inval
id.2571452619
Directory /workspace/12.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/12.pwrmgr_reset.2325387807
Short name T626
Test name
Test status
Simulation time 50716406 ps
CPU time 0.64 seconds
Started Aug 06 07:49:26 PM PDT 24
Finished Aug 06 07:49:27 PM PDT 24
Peak memory 198328 kb
Host smart-661c9f3e-e5b7-4dc5-8f97-a8784b214cab
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325387807 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset.2325387807
Directory /workspace/12.pwrmgr_reset/latest

Test location /workspace/coverage/default/12.pwrmgr_sec_cm_rstmgr_intersig_mubi.3156967352
Short name T218
Test name
Test status
Simulation time 55372416 ps
CPU time 0.78 seconds
Started Aug 06 07:49:26 PM PDT 24
Finished Aug 06 07:49:27 PM PDT 24
Peak memory 197928 kb
Host smart-fbe9fafe-b23a-402d-a0d0-e496a3ef2cb4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156967352 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3156967352
Directory /workspace/12.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/12.pwrmgr_smoke.2828707631
Short name T559
Test name
Test status
Simulation time 27004328 ps
CPU time 0.67 seconds
Started Aug 06 07:49:26 PM PDT 24
Finished Aug 06 07:49:27 PM PDT 24
Peak memory 199408 kb
Host smart-54f4b329-b330-4845-b473-301d0eb66b4e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828707631 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_smoke.2828707631
Directory /workspace/12.pwrmgr_smoke/latest

Test location /workspace/coverage/default/13.pwrmgr_aborted_low_power.2301399191
Short name T255
Test name
Test status
Simulation time 117946253 ps
CPU time 0.59 seconds
Started Aug 06 07:49:40 PM PDT 24
Finished Aug 06 07:49:41 PM PDT 24
Peak memory 198564 kb
Host smart-448da7a3-25a8-4263-b678-f21783f439ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301399191 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_aborted_low_power.2301399191
Directory /workspace/13.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/13.pwrmgr_disable_rom_integrity_check.511814041
Short name T359
Test name
Test status
Simulation time 50460495 ps
CPU time 0.76 seconds
Started Aug 06 07:49:39 PM PDT 24
Finished Aug 06 07:49:40 PM PDT 24
Peak memory 199160 kb
Host smart-2827fb1f-4ba4-41fa-9ac4-c94752e99231
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511814041 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_disa
ble_rom_integrity_check.511814041
Directory /workspace/13.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/13.pwrmgr_esc_clk_rst_malfunc.184054907
Short name T231
Test name
Test status
Simulation time 38220576 ps
CPU time 0.59 seconds
Started Aug 06 07:49:38 PM PDT 24
Finished Aug 06 07:49:38 PM PDT 24
Peak memory 198036 kb
Host smart-0db134c5-58e1-442c-b045-40506ecf7e25
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184054907 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_esc_clk_rst_
malfunc.184054907
Directory /workspace/13.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/13.pwrmgr_escalation_timeout.2276989628
Short name T565
Test name
Test status
Simulation time 607060591 ps
CPU time 0.94 seconds
Started Aug 06 07:49:39 PM PDT 24
Finished Aug 06 07:49:40 PM PDT 24
Peak memory 198156 kb
Host smart-f0f6a4c1-4a15-4898-90bc-d332629378a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276989628 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_escalation_timeout.2276989628
Directory /workspace/13.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/13.pwrmgr_glitch.3671865646
Short name T323
Test name
Test status
Simulation time 77510139 ps
CPU time 0.59 seconds
Started Aug 06 07:49:40 PM PDT 24
Finished Aug 06 07:49:41 PM PDT 24
Peak memory 197428 kb
Host smart-f70f160f-5748-486a-ad92-4b0554e5640b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671865646 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_glitch.3671865646
Directory /workspace/13.pwrmgr_glitch/latest

Test location /workspace/coverage/default/13.pwrmgr_global_esc.908224613
Short name T480
Test name
Test status
Simulation time 37621435 ps
CPU time 0.58 seconds
Started Aug 06 07:49:38 PM PDT 24
Finished Aug 06 07:49:38 PM PDT 24
Peak memory 198108 kb
Host smart-c467aecd-76be-4078-af3b-70ea5c2bc2ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908224613 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_global_esc.908224613
Directory /workspace/13.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/13.pwrmgr_lowpower_invalid.3883123873
Short name T200
Test name
Test status
Simulation time 68980248 ps
CPU time 0.65 seconds
Started Aug 06 07:49:39 PM PDT 24
Finished Aug 06 07:49:40 PM PDT 24
Peak memory 201460 kb
Host smart-cb81d63a-ade5-4dc2-ac80-314baab08116
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883123873 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_lowpower_inval
id.3883123873
Directory /workspace/13.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/13.pwrmgr_reset.3754753670
Short name T355
Test name
Test status
Simulation time 342116278 ps
CPU time 0.73 seconds
Started Aug 06 07:49:43 PM PDT 24
Finished Aug 06 07:49:44 PM PDT 24
Peak memory 198340 kb
Host smart-3e71263c-ac26-4a22-afdb-b65bd6591614
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754753670 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset.3754753670
Directory /workspace/13.pwrmgr_reset/latest

Test location /workspace/coverage/default/13.pwrmgr_reset_invalid.7118627
Short name T227
Test name
Test status
Simulation time 158536608 ps
CPU time 0.78 seconds
Started Aug 06 07:49:37 PM PDT 24
Finished Aug 06 07:49:39 PM PDT 24
Peak memory 209468 kb
Host smart-d0d0f3e0-d4f7-4386-864d-d07c8ce5441e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7118627 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset_invalid.7118627
Directory /workspace/13.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/13.pwrmgr_sec_cm_rstmgr_intersig_mubi.1798699109
Short name T250
Test name
Test status
Simulation time 87544216 ps
CPU time 0.8 seconds
Started Aug 06 07:49:38 PM PDT 24
Finished Aug 06 07:49:39 PM PDT 24
Peak memory 199316 kb
Host smart-2dc08680-6bd6-4c49-b315-fa5a0e621d8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798699109 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1798699109
Directory /workspace/13.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/13.pwrmgr_smoke.4245533969
Short name T4
Test name
Test status
Simulation time 62339654 ps
CPU time 0.63 seconds
Started Aug 06 07:49:35 PM PDT 24
Finished Aug 06 07:49:35 PM PDT 24
Peak memory 198456 kb
Host smart-55752c36-1328-477a-a9fb-f418f1753e6a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245533969 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_smoke.4245533969
Directory /workspace/13.pwrmgr_smoke/latest

Test location /workspace/coverage/default/14.pwrmgr_aborted_low_power.2788372781
Short name T526
Test name
Test status
Simulation time 35394558 ps
CPU time 0.87 seconds
Started Aug 06 07:49:41 PM PDT 24
Finished Aug 06 07:49:42 PM PDT 24
Peak memory 200264 kb
Host smart-b9735069-d505-402c-8aaa-c3ad7bb4ad9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788372781 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_aborted_low_power.2788372781
Directory /workspace/14.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/14.pwrmgr_disable_rom_integrity_check.2087832495
Short name T154
Test name
Test status
Simulation time 42749621 ps
CPU time 0.73 seconds
Started Aug 06 07:49:39 PM PDT 24
Finished Aug 06 07:49:40 PM PDT 24
Peak memory 199200 kb
Host smart-91c087cb-8699-4346-8f3d-049419abdc37
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087832495 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_dis
able_rom_integrity_check.2087832495
Directory /workspace/14.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/14.pwrmgr_esc_clk_rst_malfunc.2789726158
Short name T604
Test name
Test status
Simulation time 30586333 ps
CPU time 0.61 seconds
Started Aug 06 07:49:40 PM PDT 24
Finished Aug 06 07:49:41 PM PDT 24
Peak memory 198004 kb
Host smart-c2907204-b509-4f34-81dd-37ffd9d06547
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789726158 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_esc_clk_rst
_malfunc.2789726158
Directory /workspace/14.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/14.pwrmgr_escalation_timeout.1651622042
Short name T474
Test name
Test status
Simulation time 162527756 ps
CPU time 0.96 seconds
Started Aug 06 07:49:46 PM PDT 24
Finished Aug 06 07:49:47 PM PDT 24
Peak memory 198452 kb
Host smart-b67ecad5-c2bb-4828-92dd-caef653ae21f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651622042 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_escalation_timeout.1651622042
Directory /workspace/14.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/14.pwrmgr_global_esc.3881361149
Short name T477
Test name
Test status
Simulation time 54415952 ps
CPU time 0.59 seconds
Started Aug 06 07:49:36 PM PDT 24
Finished Aug 06 07:49:37 PM PDT 24
Peak memory 198112 kb
Host smart-34098745-508d-4b62-b0ea-f3c059916d46
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881361149 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_global_esc.3881361149
Directory /workspace/14.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/14.pwrmgr_reset.4179116310
Short name T611
Test name
Test status
Simulation time 50461150 ps
CPU time 0.62 seconds
Started Aug 06 07:49:37 PM PDT 24
Finished Aug 06 07:49:38 PM PDT 24
Peak memory 198152 kb
Host smart-b1028dfe-cade-48c5-af70-5cea65042842
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179116310 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset.4179116310
Directory /workspace/14.pwrmgr_reset/latest

Test location /workspace/coverage/default/14.pwrmgr_reset_invalid.4049414730
Short name T390
Test name
Test status
Simulation time 111920209 ps
CPU time 0.83 seconds
Started Aug 06 07:49:41 PM PDT 24
Finished Aug 06 07:49:42 PM PDT 24
Peak memory 209552 kb
Host smart-fca53077-cf17-43ae-bfe6-b1f901a58947
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049414730 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset_invalid.4049414730
Directory /workspace/14.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/14.pwrmgr_sec_cm_rstmgr_intersig_mubi.4037702991
Short name T476
Test name
Test status
Simulation time 66200659 ps
CPU time 0.84 seconds
Started Aug 06 07:49:39 PM PDT 24
Finished Aug 06 07:49:40 PM PDT 24
Peak memory 199684 kb
Host smart-882808c5-c2c5-4b13-a671-697e84e3f7f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037702991 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4037702991
Directory /workspace/14.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/14.pwrmgr_smoke.643745182
Short name T93
Test name
Test status
Simulation time 66921374 ps
CPU time 0.63 seconds
Started Aug 06 07:49:37 PM PDT 24
Finished Aug 06 07:49:38 PM PDT 24
Peak memory 198516 kb
Host smart-35d97396-2b87-4797-a03a-31c5474a51c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643745182 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_smoke.643745182
Directory /workspace/14.pwrmgr_smoke/latest

Test location /workspace/coverage/default/15.pwrmgr_aborted_low_power.2585418631
Short name T557
Test name
Test status
Simulation time 46747552 ps
CPU time 0.87 seconds
Started Aug 06 07:49:39 PM PDT 24
Finished Aug 06 07:49:40 PM PDT 24
Peak memory 200744 kb
Host smart-8a16f9a7-80f6-4d35-b80a-64407707b648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585418631 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_aborted_low_power.2585418631
Directory /workspace/15.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/15.pwrmgr_disable_rom_integrity_check.392138496
Short name T157
Test name
Test status
Simulation time 151624851 ps
CPU time 0.65 seconds
Started Aug 06 07:49:43 PM PDT 24
Finished Aug 06 07:49:44 PM PDT 24
Peak memory 198516 kb
Host smart-174da921-a318-4c50-8840-ee6a73d92134
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392138496 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_disa
ble_rom_integrity_check.392138496
Directory /workspace/15.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/15.pwrmgr_esc_clk_rst_malfunc.36564027
Short name T341
Test name
Test status
Simulation time 31234755 ps
CPU time 0.59 seconds
Started Aug 06 07:49:39 PM PDT 24
Finished Aug 06 07:49:40 PM PDT 24
Peak memory 198040 kb
Host smart-442af931-d941-4d23-bad4-504cf7dede7d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36564027 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_mal
func_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_esc_clk_rst_m
alfunc.36564027
Directory /workspace/15.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/15.pwrmgr_escalation_timeout.619814345
Short name T583
Test name
Test status
Simulation time 624513281 ps
CPU time 0.93 seconds
Started Aug 06 07:49:43 PM PDT 24
Finished Aug 06 07:49:44 PM PDT 24
Peak memory 198104 kb
Host smart-e8cdb0da-baa8-4f9d-aac8-a4dfec64fd3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619814345 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_escalation_timeout.619814345
Directory /workspace/15.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/15.pwrmgr_glitch.3891033822
Short name T235
Test name
Test status
Simulation time 89253041 ps
CPU time 0.62 seconds
Started Aug 06 07:49:46 PM PDT 24
Finished Aug 06 07:49:47 PM PDT 24
Peak memory 197412 kb
Host smart-5fe7d951-623b-489c-a482-383ed7ea1f5e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891033822 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_glitch.3891033822
Directory /workspace/15.pwrmgr_glitch/latest

Test location /workspace/coverage/default/15.pwrmgr_global_esc.110116140
Short name T351
Test name
Test status
Simulation time 43188972 ps
CPU time 0.65 seconds
Started Aug 06 07:49:43 PM PDT 24
Finished Aug 06 07:49:44 PM PDT 24
Peak memory 198116 kb
Host smart-9633b373-dbda-450e-91f5-8505e13cdc21
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110116140 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_global_esc.110116140
Directory /workspace/15.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/15.pwrmgr_lowpower_invalid.2494784231
Short name T500
Test name
Test status
Simulation time 64592185 ps
CPU time 0.65 seconds
Started Aug 06 07:49:39 PM PDT 24
Finished Aug 06 07:49:40 PM PDT 24
Peak memory 201216 kb
Host smart-45bfc5f5-1aac-43f3-95e2-d78887121e00
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494784231 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_lowpower_inval
id.2494784231
Directory /workspace/15.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/15.pwrmgr_lowpower_wakeup_race.1592276257
Short name T146
Test name
Test status
Simulation time 135515873 ps
CPU time 0.64 seconds
Started Aug 06 07:49:39 PM PDT 24
Finished Aug 06 07:49:40 PM PDT 24
Peak memory 198284 kb
Host smart-a3be0bdd-872b-4cc3-9b23-3754aaa6460e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592276257 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_lowpower_w
akeup_race.1592276257
Directory /workspace/15.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/15.pwrmgr_reset.3616671804
Short name T310
Test name
Test status
Simulation time 66085311 ps
CPU time 0.72 seconds
Started Aug 06 07:49:39 PM PDT 24
Finished Aug 06 07:49:40 PM PDT 24
Peak memory 198592 kb
Host smart-7efdf500-5e9e-4ff3-a21a-886bb41cb131
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616671804 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset.3616671804
Directory /workspace/15.pwrmgr_reset/latest

Test location /workspace/coverage/default/15.pwrmgr_reset_invalid.182936436
Short name T217
Test name
Test status
Simulation time 101873807 ps
CPU time 1.05 seconds
Started Aug 06 07:49:40 PM PDT 24
Finished Aug 06 07:49:42 PM PDT 24
Peak memory 209504 kb
Host smart-cb3be23b-54e2-4be3-afb4-ec6359a95d29
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182936436 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset_invalid.182936436
Directory /workspace/15.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/15.pwrmgr_sec_cm_rstmgr_intersig_mubi.213470181
Short name T314
Test name
Test status
Simulation time 89029103 ps
CPU time 0.78 seconds
Started Aug 06 07:49:42 PM PDT 24
Finished Aug 06 07:49:43 PM PDT 24
Peak memory 199272 kb
Host smart-5bed649e-5723-4318-9879-57b8d75ab4f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213470181 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_rstmgr_intersig_
mubi.213470181
Directory /workspace/15.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/15.pwrmgr_smoke.172942058
Short name T556
Test name
Test status
Simulation time 33610105 ps
CPU time 0.68 seconds
Started Aug 06 07:49:44 PM PDT 24
Finished Aug 06 07:49:45 PM PDT 24
Peak memory 199372 kb
Host smart-e360171b-e2fa-4b75-a5b8-2449187ef2ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172942058 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_smoke.172942058
Directory /workspace/15.pwrmgr_smoke/latest

Test location /workspace/coverage/default/16.pwrmgr_disable_rom_integrity_check.2906627600
Short name T479
Test name
Test status
Simulation time 58875152 ps
CPU time 0.68 seconds
Started Aug 06 07:49:45 PM PDT 24
Finished Aug 06 07:49:46 PM PDT 24
Peak memory 198304 kb
Host smart-49f845cd-e479-4a0e-818d-37230dbf4424
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906627600 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_dis
able_rom_integrity_check.2906627600
Directory /workspace/16.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/16.pwrmgr_esc_clk_rst_malfunc.2481242772
Short name T599
Test name
Test status
Simulation time 71957968 ps
CPU time 0.6 seconds
Started Aug 06 07:49:44 PM PDT 24
Finished Aug 06 07:49:45 PM PDT 24
Peak memory 198088 kb
Host smart-0b745213-83cc-4a35-a396-6ed5bf62d796
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481242772 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_esc_clk_rst
_malfunc.2481242772
Directory /workspace/16.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/16.pwrmgr_escalation_timeout.715687127
Short name T454
Test name
Test status
Simulation time 322322655 ps
CPU time 1.01 seconds
Started Aug 06 07:49:43 PM PDT 24
Finished Aug 06 07:49:44 PM PDT 24
Peak memory 198120 kb
Host smart-91cdec04-0d45-4397-b459-90f3293c8d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715687127 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_escalation_timeout.715687127
Directory /workspace/16.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/16.pwrmgr_glitch.119996342
Short name T17
Test name
Test status
Simulation time 45309406 ps
CPU time 0.66 seconds
Started Aug 06 07:49:44 PM PDT 24
Finished Aug 06 07:49:45 PM PDT 24
Peak memory 197360 kb
Host smart-72e490f3-d1a6-4f7e-943b-6d0d7dd93fa0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119996342 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_glitch.119996342
Directory /workspace/16.pwrmgr_glitch/latest

Test location /workspace/coverage/default/16.pwrmgr_global_esc.3360102320
Short name T309
Test name
Test status
Simulation time 45384738 ps
CPU time 0.6 seconds
Started Aug 06 07:49:44 PM PDT 24
Finished Aug 06 07:49:45 PM PDT 24
Peak memory 198128 kb
Host smart-6d5d5db8-3565-409b-9424-82119fbec5d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360102320 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_global_esc.3360102320
Directory /workspace/16.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/16.pwrmgr_reset.1020887672
Short name T411
Test name
Test status
Simulation time 62753250 ps
CPU time 0.84 seconds
Started Aug 06 07:49:39 PM PDT 24
Finished Aug 06 07:49:40 PM PDT 24
Peak memory 198972 kb
Host smart-f3ece3ce-5be6-4c8e-b484-d0608b11e069
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020887672 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset.1020887672
Directory /workspace/16.pwrmgr_reset/latest

Test location /workspace/coverage/default/16.pwrmgr_reset_invalid.2513138580
Short name T37
Test name
Test status
Simulation time 497439424 ps
CPU time 0.81 seconds
Started Aug 06 07:49:42 PM PDT 24
Finished Aug 06 07:49:43 PM PDT 24
Peak memory 209540 kb
Host smart-269d3430-a551-4fe2-9914-528958f5b07c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513138580 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset_invalid.2513138580
Directory /workspace/16.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/16.pwrmgr_sec_cm_rstmgr_intersig_mubi.2192206062
Short name T269
Test name
Test status
Simulation time 53892223 ps
CPU time 0.84 seconds
Started Aug 06 07:49:45 PM PDT 24
Finished Aug 06 07:49:46 PM PDT 24
Peak memory 199276 kb
Host smart-17008e0a-5916-470c-92fd-29e041341990
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192206062 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2192206062
Directory /workspace/16.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/16.pwrmgr_smoke.3864703200
Short name T94
Test name
Test status
Simulation time 33678830 ps
CPU time 0.65 seconds
Started Aug 06 07:49:43 PM PDT 24
Finished Aug 06 07:49:44 PM PDT 24
Peak memory 199252 kb
Host smart-68210614-068b-460b-9939-821465ad6030
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864703200 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_smoke.3864703200
Directory /workspace/16.pwrmgr_smoke/latest

Test location /workspace/coverage/default/17.pwrmgr_aborted_low_power.2820654841
Short name T386
Test name
Test status
Simulation time 41887052 ps
CPU time 0.78 seconds
Started Aug 06 07:49:45 PM PDT 24
Finished Aug 06 07:49:46 PM PDT 24
Peak memory 198864 kb
Host smart-a120bfec-37de-4e43-baf7-197b59f8dd86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820654841 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_aborted_low_power.2820654841
Directory /workspace/17.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/17.pwrmgr_disable_rom_integrity_check.903961920
Short name T514
Test name
Test status
Simulation time 76443518 ps
CPU time 0.66 seconds
Started Aug 06 07:49:46 PM PDT 24
Finished Aug 06 07:49:47 PM PDT 24
Peak memory 198388 kb
Host smart-ffd5a868-7cc8-4dfd-a07e-f8b029ae2735
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903961920 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_disa
ble_rom_integrity_check.903961920
Directory /workspace/17.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/17.pwrmgr_esc_clk_rst_malfunc.886525285
Short name T378
Test name
Test status
Simulation time 31343537 ps
CPU time 0.61 seconds
Started Aug 06 07:49:45 PM PDT 24
Finished Aug 06 07:49:46 PM PDT 24
Peak memory 198024 kb
Host smart-8f3f5fda-6d00-4a27-8f5b-ef3fae0564d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886525285 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_esc_clk_rst_
malfunc.886525285
Directory /workspace/17.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/17.pwrmgr_escalation_timeout.1897933195
Short name T418
Test name
Test status
Simulation time 163074989 ps
CPU time 0.96 seconds
Started Aug 06 07:49:47 PM PDT 24
Finished Aug 06 07:49:48 PM PDT 24
Peak memory 198012 kb
Host smart-4d643e82-2233-4b2c-bc37-54dedac37629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897933195 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_escalation_timeout.1897933195
Directory /workspace/17.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/17.pwrmgr_glitch.2265869077
Short name T612
Test name
Test status
Simulation time 39314912 ps
CPU time 0.6 seconds
Started Aug 06 07:49:51 PM PDT 24
Finished Aug 06 07:49:51 PM PDT 24
Peak memory 197964 kb
Host smart-92dcc014-47fe-4cd8-a931-163a3db3c473
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265869077 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_glitch.2265869077
Directory /workspace/17.pwrmgr_glitch/latest

Test location /workspace/coverage/default/17.pwrmgr_global_esc.3878241550
Short name T617
Test name
Test status
Simulation time 56459965 ps
CPU time 0.66 seconds
Started Aug 06 07:49:41 PM PDT 24
Finished Aug 06 07:49:42 PM PDT 24
Peak memory 198100 kb
Host smart-9e266248-fcb2-4bbb-a8c5-381166508893
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878241550 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_global_esc.3878241550
Directory /workspace/17.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/17.pwrmgr_lowpower_invalid.3709515823
Short name T193
Test name
Test status
Simulation time 46114996 ps
CPU time 0.71 seconds
Started Aug 06 07:49:41 PM PDT 24
Finished Aug 06 07:49:42 PM PDT 24
Peak memory 201408 kb
Host smart-8d5bff79-3b3f-4f98-97b0-41891cb7c000
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709515823 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_lowpower_inval
id.3709515823
Directory /workspace/17.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/17.pwrmgr_reset.1771521082
Short name T592
Test name
Test status
Simulation time 54951226 ps
CPU time 0.83 seconds
Started Aug 06 07:49:47 PM PDT 24
Finished Aug 06 07:49:48 PM PDT 24
Peak memory 199408 kb
Host smart-46849dec-9444-42ac-8ba9-16a5e6df05a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771521082 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset.1771521082
Directory /workspace/17.pwrmgr_reset/latest

Test location /workspace/coverage/default/17.pwrmgr_reset_invalid.2617252619
Short name T1
Test name
Test status
Simulation time 428871305 ps
CPU time 0.79 seconds
Started Aug 06 07:49:46 PM PDT 24
Finished Aug 06 07:49:47 PM PDT 24
Peak memory 209460 kb
Host smart-a0395154-ad7e-4b41-b4b3-913e3851b724
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617252619 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset_invalid.2617252619
Directory /workspace/17.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/17.pwrmgr_sec_cm_rstmgr_intersig_mubi.1912732639
Short name T268
Test name
Test status
Simulation time 104384757 ps
CPU time 0.76 seconds
Started Aug 06 07:49:44 PM PDT 24
Finished Aug 06 07:49:45 PM PDT 24
Peak memory 197968 kb
Host smart-1c6a9047-0957-4375-98ac-73edc4a218e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912732639 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1912732639
Directory /workspace/17.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/17.pwrmgr_smoke.935633176
Short name T328
Test name
Test status
Simulation time 57853076 ps
CPU time 0.66 seconds
Started Aug 06 07:49:48 PM PDT 24
Finished Aug 06 07:49:49 PM PDT 24
Peak memory 198764 kb
Host smart-e0a19ffb-90f9-420d-8722-5b5b88a7b41a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935633176 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_smoke.935633176
Directory /workspace/17.pwrmgr_smoke/latest

Test location /workspace/coverage/default/18.pwrmgr_aborted_low_power.3253432774
Short name T59
Test name
Test status
Simulation time 22692908 ps
CPU time 0.79 seconds
Started Aug 06 07:49:47 PM PDT 24
Finished Aug 06 07:49:48 PM PDT 24
Peak memory 199832 kb
Host smart-98fa86c9-f683-4a12-b8e9-47e83d8e0596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253432774 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_aborted_low_power.3253432774
Directory /workspace/18.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/18.pwrmgr_disable_rom_integrity_check.2832469550
Short name T544
Test name
Test status
Simulation time 55750447 ps
CPU time 0.79 seconds
Started Aug 06 07:49:44 PM PDT 24
Finished Aug 06 07:49:45 PM PDT 24
Peak memory 199076 kb
Host smart-405d10f7-b0c4-412a-8502-c7276f6a14e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832469550 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_dis
able_rom_integrity_check.2832469550
Directory /workspace/18.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/18.pwrmgr_esc_clk_rst_malfunc.2216355390
Short name T406
Test name
Test status
Simulation time 30088614 ps
CPU time 0.61 seconds
Started Aug 06 07:49:45 PM PDT 24
Finished Aug 06 07:49:46 PM PDT 24
Peak memory 198064 kb
Host smart-3f4ea38d-8f04-427e-8037-9f439ee0daf0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216355390 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_esc_clk_rst
_malfunc.2216355390
Directory /workspace/18.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/18.pwrmgr_escalation_timeout.2597105705
Short name T240
Test name
Test status
Simulation time 303343657 ps
CPU time 0.94 seconds
Started Aug 06 07:49:42 PM PDT 24
Finished Aug 06 07:49:43 PM PDT 24
Peak memory 198132 kb
Host smart-12f6b2d9-e453-4474-9343-5c794d59091e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597105705 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_escalation_timeout.2597105705
Directory /workspace/18.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/18.pwrmgr_glitch.1383979753
Short name T368
Test name
Test status
Simulation time 50232314 ps
CPU time 0.69 seconds
Started Aug 06 07:49:42 PM PDT 24
Finished Aug 06 07:49:43 PM PDT 24
Peak memory 197344 kb
Host smart-0766506d-8679-41c0-a722-2431ec627194
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383979753 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_glitch.1383979753
Directory /workspace/18.pwrmgr_glitch/latest

Test location /workspace/coverage/default/18.pwrmgr_global_esc.2837438711
Short name T496
Test name
Test status
Simulation time 327634820 ps
CPU time 0.62 seconds
Started Aug 06 07:49:40 PM PDT 24
Finished Aug 06 07:49:41 PM PDT 24
Peak memory 198368 kb
Host smart-a068415d-e942-4087-a7e6-dad2297687c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837438711 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_global_esc.2837438711
Directory /workspace/18.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/18.pwrmgr_reset.2438757470
Short name T313
Test name
Test status
Simulation time 53259810 ps
CPU time 0.79 seconds
Started Aug 06 07:49:45 PM PDT 24
Finished Aug 06 07:49:46 PM PDT 24
Peak memory 199064 kb
Host smart-46d632a5-d65b-4982-828e-ed8e3e41a2ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438757470 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset.2438757470
Directory /workspace/18.pwrmgr_reset/latest

Test location /workspace/coverage/default/18.pwrmgr_reset_invalid.417122854
Short name T271
Test name
Test status
Simulation time 163799144 ps
CPU time 0.8 seconds
Started Aug 06 07:49:41 PM PDT 24
Finished Aug 06 07:49:42 PM PDT 24
Peak memory 209548 kb
Host smart-6805a65b-795e-4ea6-8eba-aa21e91d21c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417122854 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset_invalid.417122854
Directory /workspace/18.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/18.pwrmgr_sec_cm_rstmgr_intersig_mubi.3180518452
Short name T303
Test name
Test status
Simulation time 236868719 ps
CPU time 0.77 seconds
Started Aug 06 07:49:40 PM PDT 24
Finished Aug 06 07:49:41 PM PDT 24
Peak memory 199172 kb
Host smart-cf94c537-8248-4bef-b5d8-142658bb9798
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180518452 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3180518452
Directory /workspace/18.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/18.pwrmgr_smoke.3208600857
Short name T458
Test name
Test status
Simulation time 40130994 ps
CPU time 0.66 seconds
Started Aug 06 07:49:45 PM PDT 24
Finished Aug 06 07:49:46 PM PDT 24
Peak memory 199344 kb
Host smart-07a72f5a-9391-4bd8-bf26-6d2048747ff5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208600857 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_smoke.3208600857
Directory /workspace/18.pwrmgr_smoke/latest

Test location /workspace/coverage/default/19.pwrmgr_aborted_low_power.3188630258
Short name T98
Test name
Test status
Simulation time 26492651 ps
CPU time 0.63 seconds
Started Aug 06 07:49:43 PM PDT 24
Finished Aug 06 07:49:44 PM PDT 24
Peak memory 199176 kb
Host smart-7e0020f1-84c4-4475-ab69-b57ad5e38ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188630258 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_aborted_low_power.3188630258
Directory /workspace/19.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/19.pwrmgr_disable_rom_integrity_check.545827994
Short name T167
Test name
Test status
Simulation time 54668985 ps
CPU time 0.8 seconds
Started Aug 06 07:49:44 PM PDT 24
Finished Aug 06 07:49:46 PM PDT 24
Peak memory 199196 kb
Host smart-8c16c06d-5573-4fc4-acfa-13772b8e26e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545827994 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_disa
ble_rom_integrity_check.545827994
Directory /workspace/19.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/19.pwrmgr_esc_clk_rst_malfunc.1093663655
Short name T11
Test name
Test status
Simulation time 38479614 ps
CPU time 0.6 seconds
Started Aug 06 07:49:46 PM PDT 24
Finished Aug 06 07:49:47 PM PDT 24
Peak memory 197988 kb
Host smart-d5925f7e-88e1-4618-be06-0ffc77d80dc0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093663655 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_esc_clk_rst
_malfunc.1093663655
Directory /workspace/19.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/19.pwrmgr_escalation_timeout.2821511720
Short name T243
Test name
Test status
Simulation time 162518624 ps
CPU time 0.93 seconds
Started Aug 06 07:49:44 PM PDT 24
Finished Aug 06 07:49:45 PM PDT 24
Peak memory 198412 kb
Host smart-d04c7d3a-d0cf-4d56-a253-605407f85d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821511720 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_escalation_timeout.2821511720
Directory /workspace/19.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/19.pwrmgr_glitch.3081339011
Short name T397
Test name
Test status
Simulation time 29066916 ps
CPU time 0.65 seconds
Started Aug 06 07:49:45 PM PDT 24
Finished Aug 06 07:49:46 PM PDT 24
Peak memory 197424 kb
Host smart-f4234664-eb4e-41d6-ae8b-5d5be20beaa9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081339011 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_glitch.3081339011
Directory /workspace/19.pwrmgr_glitch/latest

Test location /workspace/coverage/default/19.pwrmgr_global_esc.1405016318
Short name T215
Test name
Test status
Simulation time 64803673 ps
CPU time 0.59 seconds
Started Aug 06 07:49:44 PM PDT 24
Finished Aug 06 07:49:45 PM PDT 24
Peak memory 198084 kb
Host smart-f6aba536-5d5d-409e-ae81-924ef03bab7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405016318 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_global_esc.1405016318
Directory /workspace/19.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/19.pwrmgr_lowpower_invalid.1024710310
Short name T53
Test name
Test status
Simulation time 136300450 ps
CPU time 0.64 seconds
Started Aug 06 07:49:46 PM PDT 24
Finished Aug 06 07:49:47 PM PDT 24
Peak memory 201444 kb
Host smart-3cc54eb5-8b32-4fd1-815e-59c26b59c8cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024710310 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_lowpower_inval
id.1024710310
Directory /workspace/19.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/19.pwrmgr_reset.511026621
Short name T402
Test name
Test status
Simulation time 62856770 ps
CPU time 0.72 seconds
Started Aug 06 07:49:43 PM PDT 24
Finished Aug 06 07:49:44 PM PDT 24
Peak memory 199240 kb
Host smart-8fade05b-0014-433b-b66c-5f80b26efedb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511026621 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset.511026621
Directory /workspace/19.pwrmgr_reset/latest

Test location /workspace/coverage/default/19.pwrmgr_reset_invalid.2854545131
Short name T306
Test name
Test status
Simulation time 249689727 ps
CPU time 0.76 seconds
Started Aug 06 07:49:43 PM PDT 24
Finished Aug 06 07:49:44 PM PDT 24
Peak memory 209576 kb
Host smart-b90fb41c-8ddb-434b-be66-afaab11f3e67
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854545131 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset_invalid.2854545131
Directory /workspace/19.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/19.pwrmgr_sec_cm_rstmgr_intersig_mubi.2539486144
Short name T581
Test name
Test status
Simulation time 136934448 ps
CPU time 0.83 seconds
Started Aug 06 07:49:42 PM PDT 24
Finished Aug 06 07:49:43 PM PDT 24
Peak memory 199188 kb
Host smart-8c28df98-b961-4f35-a115-aadb99e65388
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539486144 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2539486144
Directory /workspace/19.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/19.pwrmgr_smoke.1818483331
Short name T387
Test name
Test status
Simulation time 31192411 ps
CPU time 0.68 seconds
Started Aug 06 07:49:45 PM PDT 24
Finished Aug 06 07:49:46 PM PDT 24
Peak memory 199384 kb
Host smart-c16de096-775d-4f54-8ed9-3275239d2a45
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818483331 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_smoke.1818483331
Directory /workspace/19.pwrmgr_smoke/latest

Test location /workspace/coverage/default/2.pwrmgr_aborted_low_power.891619044
Short name T394
Test name
Test status
Simulation time 49135611 ps
CPU time 0.95 seconds
Started Aug 06 07:48:34 PM PDT 24
Finished Aug 06 07:48:35 PM PDT 24
Peak memory 200144 kb
Host smart-803d7814-cfd8-4c66-8c65-9b8822366472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891619044 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_aborted_low_power.891619044
Directory /workspace/2.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/2.pwrmgr_disable_rom_integrity_check.3782221455
Short name T462
Test name
Test status
Simulation time 116524113 ps
CPU time 0.64 seconds
Started Aug 06 07:48:33 PM PDT 24
Finished Aug 06 07:48:34 PM PDT 24
Peak memory 198472 kb
Host smart-55cb6b1f-ca9e-4f09-b3f7-82b9faf3e708
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782221455 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_disa
ble_rom_integrity_check.3782221455
Directory /workspace/2.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/2.pwrmgr_esc_clk_rst_malfunc.1023651657
Short name T299
Test name
Test status
Simulation time 32538192 ps
CPU time 0.62 seconds
Started Aug 06 07:48:44 PM PDT 24
Finished Aug 06 07:48:45 PM PDT 24
Peak memory 198028 kb
Host smart-ffa2ac67-5552-47e7-9192-306b579d377e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023651657 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_esc_clk_rst_
malfunc.1023651657
Directory /workspace/2.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/2.pwrmgr_escalation_timeout.3061028824
Short name T597
Test name
Test status
Simulation time 636158958 ps
CPU time 0.95 seconds
Started Aug 06 07:48:44 PM PDT 24
Finished Aug 06 07:48:45 PM PDT 24
Peak memory 198396 kb
Host smart-eb3a27d5-a693-4abb-ad1a-a2d6ac42aba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061028824 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_escalation_timeout.3061028824
Directory /workspace/2.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/2.pwrmgr_glitch.1220605534
Short name T316
Test name
Test status
Simulation time 41397867 ps
CPU time 0.65 seconds
Started Aug 06 07:48:47 PM PDT 24
Finished Aug 06 07:48:47 PM PDT 24
Peak memory 197440 kb
Host smart-4406b0a4-c023-46cd-b96f-2b0d8e31b25d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220605534 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_glitch.1220605534
Directory /workspace/2.pwrmgr_glitch/latest

Test location /workspace/coverage/default/2.pwrmgr_global_esc.2927260520
Short name T262
Test name
Test status
Simulation time 98967717 ps
CPU time 0.64 seconds
Started Aug 06 07:48:42 PM PDT 24
Finished Aug 06 07:48:43 PM PDT 24
Peak memory 198016 kb
Host smart-5f258a52-7def-49c7-9bee-aeea4ee2e4c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927260520 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_global_esc.2927260520
Directory /workspace/2.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/2.pwrmgr_lowpower_invalid.3025205940
Short name T195
Test name
Test status
Simulation time 50890022 ps
CPU time 0.67 seconds
Started Aug 06 07:48:46 PM PDT 24
Finished Aug 06 07:48:47 PM PDT 24
Peak memory 201368 kb
Host smart-4478ae31-ff72-4e57-a5f0-0770d3a7e755
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025205940 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_lowpower_invali
d.3025205940
Directory /workspace/2.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/2.pwrmgr_reset.3364798621
Short name T47
Test name
Test status
Simulation time 36286738 ps
CPU time 0.62 seconds
Started Aug 06 07:48:44 PM PDT 24
Finished Aug 06 07:48:44 PM PDT 24
Peak memory 198144 kb
Host smart-854ffa84-6f11-4cee-885f-375aa34ae046
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364798621 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset.3364798621
Directory /workspace/2.pwrmgr_reset/latest

Test location /workspace/coverage/default/2.pwrmgr_reset_invalid.2521089077
Short name T562
Test name
Test status
Simulation time 447507168 ps
CPU time 0.84 seconds
Started Aug 06 07:48:42 PM PDT 24
Finished Aug 06 07:48:43 PM PDT 24
Peak memory 209528 kb
Host smart-4a57e74e-d6b3-4c4b-9632-7878a1ea4170
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521089077 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset_invalid.2521089077
Directory /workspace/2.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm.23721749
Short name T20
Test name
Test status
Simulation time 634149002 ps
CPU time 1.01 seconds
Started Aug 06 07:48:30 PM PDT 24
Finished Aug 06 07:48:32 PM PDT 24
Peak memory 216812 kb
Host smart-e2f6e0cb-df1f-4710-a3d8-1c91b814245b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23721749 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm.23721749
Directory /workspace/2.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm_rstmgr_intersig_mubi.4220670103
Short name T563
Test name
Test status
Simulation time 91819089 ps
CPU time 0.67 seconds
Started Aug 06 07:48:42 PM PDT 24
Finished Aug 06 07:48:43 PM PDT 24
Peak memory 198204 kb
Host smart-f7852965-9ec8-476b-85c9-eef7f551312e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220670103 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm_rstmgr_intersig_
mubi.4220670103
Directory /workspace/2.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/2.pwrmgr_smoke.3913208701
Short name T582
Test name
Test status
Simulation time 28902751 ps
CPU time 0.68 seconds
Started Aug 06 07:48:30 PM PDT 24
Finished Aug 06 07:48:31 PM PDT 24
Peak memory 198532 kb
Host smart-9865739a-53e8-4d26-906a-18af44d031cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913208701 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_smoke.3913208701
Directory /workspace/2.pwrmgr_smoke/latest

Test location /workspace/coverage/default/20.pwrmgr_aborted_low_power.3873755921
Short name T340
Test name
Test status
Simulation time 54298153 ps
CPU time 0.89 seconds
Started Aug 06 07:49:46 PM PDT 24
Finished Aug 06 07:49:47 PM PDT 24
Peak memory 200032 kb
Host smart-d688c58f-cf5e-4977-b5cc-313d180f5f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873755921 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_aborted_low_power.3873755921
Directory /workspace/20.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/20.pwrmgr_disable_rom_integrity_check.899073821
Short name T139
Test name
Test status
Simulation time 64075537 ps
CPU time 0.69 seconds
Started Aug 06 07:49:40 PM PDT 24
Finished Aug 06 07:49:41 PM PDT 24
Peak memory 199180 kb
Host smart-f5a3dcb0-ddb2-4044-b7cc-09c076fd2435
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899073821 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_disa
ble_rom_integrity_check.899073821
Directory /workspace/20.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/20.pwrmgr_esc_clk_rst_malfunc.430979383
Short name T32
Test name
Test status
Simulation time 37139171 ps
CPU time 0.59 seconds
Started Aug 06 07:49:47 PM PDT 24
Finished Aug 06 07:49:47 PM PDT 24
Peak memory 198044 kb
Host smart-1d7ea5c4-360b-4706-bd39-36d512a04e9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430979383 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_esc_clk_rst_
malfunc.430979383
Directory /workspace/20.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/20.pwrmgr_escalation_timeout.2703330382
Short name T381
Test name
Test status
Simulation time 555093093 ps
CPU time 0.94 seconds
Started Aug 06 07:49:45 PM PDT 24
Finished Aug 06 07:49:46 PM PDT 24
Peak memory 198064 kb
Host smart-c98c8dba-d415-4b68-8f25-4b470628827c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703330382 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_escalation_timeout.2703330382
Directory /workspace/20.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/20.pwrmgr_glitch.2240630912
Short name T499
Test name
Test status
Simulation time 44798223 ps
CPU time 0.63 seconds
Started Aug 06 07:49:44 PM PDT 24
Finished Aug 06 07:49:45 PM PDT 24
Peak memory 198096 kb
Host smart-9a0c66d0-5f65-4fc1-bba1-e1127aadcee8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240630912 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_glitch.2240630912
Directory /workspace/20.pwrmgr_glitch/latest

Test location /workspace/coverage/default/20.pwrmgr_global_esc.2399053456
Short name T352
Test name
Test status
Simulation time 82975494 ps
CPU time 0.61 seconds
Started Aug 06 07:49:44 PM PDT 24
Finished Aug 06 07:49:45 PM PDT 24
Peak memory 198388 kb
Host smart-3b936377-661c-4947-b928-6dba33c33a76
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399053456 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_global_esc.2399053456
Directory /workspace/20.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/20.pwrmgr_reset.4261425195
Short name T210
Test name
Test status
Simulation time 61190976 ps
CPU time 0.83 seconds
Started Aug 06 07:49:41 PM PDT 24
Finished Aug 06 07:49:42 PM PDT 24
Peak memory 199120 kb
Host smart-18a171a6-da27-4529-b342-1b57cb9b81ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261425195 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset.4261425195
Directory /workspace/20.pwrmgr_reset/latest

Test location /workspace/coverage/default/20.pwrmgr_reset_invalid.433080486
Short name T315
Test name
Test status
Simulation time 142841366 ps
CPU time 0.83 seconds
Started Aug 06 07:49:45 PM PDT 24
Finished Aug 06 07:49:46 PM PDT 24
Peak memory 209408 kb
Host smart-4ae03635-da15-48d0-9500-eca4dcdf7f04
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433080486 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset_invalid.433080486
Directory /workspace/20.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/20.pwrmgr_sec_cm_rstmgr_intersig_mubi.2847639898
Short name T577
Test name
Test status
Simulation time 52819979 ps
CPU time 0.8 seconds
Started Aug 06 07:49:44 PM PDT 24
Finished Aug 06 07:49:45 PM PDT 24
Peak memory 198124 kb
Host smart-6d09f339-837b-4efe-8eb6-401f9242b620
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847639898 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2847639898
Directory /workspace/20.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/20.pwrmgr_smoke.3611918297
Short name T33
Test name
Test status
Simulation time 60538716 ps
CPU time 0.62 seconds
Started Aug 06 07:49:42 PM PDT 24
Finished Aug 06 07:49:43 PM PDT 24
Peak memory 198572 kb
Host smart-d0aeb99e-c7a8-4112-938d-25502154541a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611918297 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_smoke.3611918297
Directory /workspace/20.pwrmgr_smoke/latest

Test location /workspace/coverage/default/21.pwrmgr_aborted_low_power.345501587
Short name T308
Test name
Test status
Simulation time 111750257 ps
CPU time 0.71 seconds
Started Aug 06 07:49:42 PM PDT 24
Finished Aug 06 07:49:43 PM PDT 24
Peak memory 198656 kb
Host smart-9fa773a1-cfa0-4868-b17c-d25421e98b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345501587 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_aborted_low_power.345501587
Directory /workspace/21.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/21.pwrmgr_disable_rom_integrity_check.225643370
Short name T484
Test name
Test status
Simulation time 98376463 ps
CPU time 0.71 seconds
Started Aug 06 07:49:43 PM PDT 24
Finished Aug 06 07:49:44 PM PDT 24
Peak memory 198592 kb
Host smart-7801ed1f-afdc-49d9-9199-669d8cbaa665
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225643370 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_disa
ble_rom_integrity_check.225643370
Directory /workspace/21.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/21.pwrmgr_esc_clk_rst_malfunc.2933669103
Short name T622
Test name
Test status
Simulation time 37668247 ps
CPU time 0.59 seconds
Started Aug 06 07:49:43 PM PDT 24
Finished Aug 06 07:49:44 PM PDT 24
Peak memory 197932 kb
Host smart-9e1f05c2-037f-43a9-80a1-b8567d3cf723
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933669103 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_esc_clk_rst
_malfunc.2933669103
Directory /workspace/21.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/21.pwrmgr_escalation_timeout.1676307220
Short name T568
Test name
Test status
Simulation time 541813648 ps
CPU time 0.98 seconds
Started Aug 06 07:49:44 PM PDT 24
Finished Aug 06 07:49:45 PM PDT 24
Peak memory 198420 kb
Host smart-7087e367-73c8-4f14-9a9a-657cddd4ebc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676307220 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_escalation_timeout.1676307220
Directory /workspace/21.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/21.pwrmgr_glitch.215449058
Short name T288
Test name
Test status
Simulation time 39775181 ps
CPU time 0.63 seconds
Started Aug 06 07:49:46 PM PDT 24
Finished Aug 06 07:49:47 PM PDT 24
Peak memory 198068 kb
Host smart-62fec4be-8771-4714-961d-8ca035553e40
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215449058 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_glitch.215449058
Directory /workspace/21.pwrmgr_glitch/latest

Test location /workspace/coverage/default/21.pwrmgr_global_esc.577776662
Short name T214
Test name
Test status
Simulation time 28693704 ps
CPU time 0.61 seconds
Started Aug 06 07:49:42 PM PDT 24
Finished Aug 06 07:49:42 PM PDT 24
Peak memory 198120 kb
Host smart-0c98f736-5b7e-4e55-a96c-f7db78a85ef9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577776662 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_global_esc.577776662
Directory /workspace/21.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/21.pwrmgr_reset.2358794779
Short name T292
Test name
Test status
Simulation time 82651933 ps
CPU time 0.77 seconds
Started Aug 06 07:49:45 PM PDT 24
Finished Aug 06 07:49:46 PM PDT 24
Peak memory 199076 kb
Host smart-13d6815d-071a-4f1f-a8f9-6c688577c189
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358794779 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset.2358794779
Directory /workspace/21.pwrmgr_reset/latest

Test location /workspace/coverage/default/21.pwrmgr_reset_invalid.2004447252
Short name T291
Test name
Test status
Simulation time 117596742 ps
CPU time 0.85 seconds
Started Aug 06 07:49:44 PM PDT 24
Finished Aug 06 07:49:45 PM PDT 24
Peak memory 209524 kb
Host smart-163efe7a-3804-4a85-b762-f504acf2c1c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004447252 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset_invalid.2004447252
Directory /workspace/21.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/21.pwrmgr_sec_cm_rstmgr_intersig_mubi.3287279803
Short name T38
Test name
Test status
Simulation time 62153507 ps
CPU time 0.86 seconds
Started Aug 06 07:49:42 PM PDT 24
Finished Aug 06 07:49:43 PM PDT 24
Peak memory 198096 kb
Host smart-d29c6e9e-7a74-4c44-899e-61894dddb31f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287279803 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3287279803
Directory /workspace/21.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/21.pwrmgr_smoke.3355552155
Short name T371
Test name
Test status
Simulation time 58769869 ps
CPU time 0.65 seconds
Started Aug 06 07:49:41 PM PDT 24
Finished Aug 06 07:49:42 PM PDT 24
Peak memory 198492 kb
Host smart-260f5831-e423-4c31-9441-7520f2a9a798
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355552155 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_smoke.3355552155
Directory /workspace/21.pwrmgr_smoke/latest

Test location /workspace/coverage/default/22.pwrmgr_aborted_low_power.776546867
Short name T345
Test name
Test status
Simulation time 147510309 ps
CPU time 0.63 seconds
Started Aug 06 07:49:44 PM PDT 24
Finished Aug 06 07:49:45 PM PDT 24
Peak memory 198588 kb
Host smart-513a1c74-316e-4a18-9860-1dbc5ea1cfa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776546867 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_aborted_low_power.776546867
Directory /workspace/22.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/22.pwrmgr_disable_rom_integrity_check.2960748761
Short name T627
Test name
Test status
Simulation time 62557375 ps
CPU time 0.68 seconds
Started Aug 06 07:49:50 PM PDT 24
Finished Aug 06 07:49:51 PM PDT 24
Peak memory 198964 kb
Host smart-49466584-bb13-4386-a441-e98b03b9b4a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960748761 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_dis
able_rom_integrity_check.2960748761
Directory /workspace/22.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/22.pwrmgr_escalation_timeout.2851989364
Short name T537
Test name
Test status
Simulation time 602263018 ps
CPU time 0.93 seconds
Started Aug 06 07:49:59 PM PDT 24
Finished Aug 06 07:50:00 PM PDT 24
Peak memory 198196 kb
Host smart-f44f766d-6d17-48c1-94be-7d345cc40d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851989364 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_escalation_timeout.2851989364
Directory /workspace/22.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/22.pwrmgr_glitch.3027297486
Short name T513
Test name
Test status
Simulation time 166577304 ps
CPU time 0.6 seconds
Started Aug 06 07:49:59 PM PDT 24
Finished Aug 06 07:50:00 PM PDT 24
Peak memory 198072 kb
Host smart-4afd78d3-374d-4a21-92a3-369aaf7ae6f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027297486 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_glitch.3027297486
Directory /workspace/22.pwrmgr_glitch/latest

Test location /workspace/coverage/default/22.pwrmgr_global_esc.581904267
Short name T586
Test name
Test status
Simulation time 50542254 ps
CPU time 0.63 seconds
Started Aug 06 07:49:55 PM PDT 24
Finished Aug 06 07:49:56 PM PDT 24
Peak memory 198116 kb
Host smart-df770aee-9ab2-41d9-8a2a-0b0d5d4550bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581904267 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_global_esc.581904267
Directory /workspace/22.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/22.pwrmgr_reset.1591153210
Short name T460
Test name
Test status
Simulation time 25101859 ps
CPU time 0.62 seconds
Started Aug 06 07:49:44 PM PDT 24
Finished Aug 06 07:49:45 PM PDT 24
Peak memory 199180 kb
Host smart-60fc71a9-cf48-4e33-b446-ceda8d2c9273
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591153210 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset.1591153210
Directory /workspace/22.pwrmgr_reset/latest

Test location /workspace/coverage/default/22.pwrmgr_reset_invalid.2301612282
Short name T623
Test name
Test status
Simulation time 95351234 ps
CPU time 1.06 seconds
Started Aug 06 07:49:59 PM PDT 24
Finished Aug 06 07:50:01 PM PDT 24
Peak memory 209516 kb
Host smart-249c9aa3-bc19-4397-aeca-ca8a6f34820d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301612282 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset_invalid.2301612282
Directory /workspace/22.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/22.pwrmgr_sec_cm_rstmgr_intersig_mubi.3507712621
Short name T591
Test name
Test status
Simulation time 50540340 ps
CPU time 0.8 seconds
Started Aug 06 07:49:45 PM PDT 24
Finished Aug 06 07:49:47 PM PDT 24
Peak memory 198144 kb
Host smart-802e9fd2-4573-4d2a-9640-fd26c3db5e5b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507712621 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3507712621
Directory /workspace/22.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/22.pwrmgr_smoke.4288809177
Short name T585
Test name
Test status
Simulation time 56097545 ps
CPU time 0.64 seconds
Started Aug 06 07:49:46 PM PDT 24
Finished Aug 06 07:49:47 PM PDT 24
Peak memory 199316 kb
Host smart-8da45ad7-4a1a-49b5-8173-7336eff1c657
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288809177 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_smoke.4288809177
Directory /workspace/22.pwrmgr_smoke/latest

Test location /workspace/coverage/default/23.pwrmgr_aborted_low_power.517621945
Short name T102
Test name
Test status
Simulation time 53141332 ps
CPU time 1.01 seconds
Started Aug 06 07:50:01 PM PDT 24
Finished Aug 06 07:50:02 PM PDT 24
Peak memory 200268 kb
Host smart-284b07a7-c3bc-497f-af01-e7478a46c8f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517621945 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_aborted_low_power.517621945
Directory /workspace/23.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/23.pwrmgr_disable_rom_integrity_check.773631198
Short name T464
Test name
Test status
Simulation time 58333532 ps
CPU time 0.7 seconds
Started Aug 06 07:49:59 PM PDT 24
Finished Aug 06 07:50:00 PM PDT 24
Peak memory 199188 kb
Host smart-201ed979-ff31-43a4-a913-b5ce8eb6a28a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773631198 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_disa
ble_rom_integrity_check.773631198
Directory /workspace/23.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/23.pwrmgr_esc_clk_rst_malfunc.904421952
Short name T134
Test name
Test status
Simulation time 39758040 ps
CPU time 0.59 seconds
Started Aug 06 07:50:00 PM PDT 24
Finished Aug 06 07:50:01 PM PDT 24
Peak memory 196604 kb
Host smart-f7b01371-bf52-412f-b448-4d9a85dcd5b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904421952 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_esc_clk_rst_
malfunc.904421952
Directory /workspace/23.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/23.pwrmgr_escalation_timeout.236768239
Short name T425
Test name
Test status
Simulation time 325456165 ps
CPU time 0.95 seconds
Started Aug 06 07:49:59 PM PDT 24
Finished Aug 06 07:50:00 PM PDT 24
Peak memory 198108 kb
Host smart-1390c46c-2977-42b1-8f40-fd80114d6a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236768239 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_escalation_timeout.236768239
Directory /workspace/23.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/23.pwrmgr_glitch.2020588458
Short name T424
Test name
Test status
Simulation time 39077061 ps
CPU time 0.67 seconds
Started Aug 06 07:50:03 PM PDT 24
Finished Aug 06 07:50:04 PM PDT 24
Peak memory 198036 kb
Host smart-7bba7e35-daf9-41e9-b24e-2c1c77abab56
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020588458 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_glitch.2020588458
Directory /workspace/23.pwrmgr_glitch/latest

Test location /workspace/coverage/default/23.pwrmgr_global_esc.3533582697
Short name T399
Test name
Test status
Simulation time 67444489 ps
CPU time 0.64 seconds
Started Aug 06 07:50:02 PM PDT 24
Finished Aug 06 07:50:03 PM PDT 24
Peak memory 198488 kb
Host smart-06decb0f-90ac-4cbf-84fc-faefe6933979
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533582697 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_global_esc.3533582697
Directory /workspace/23.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/23.pwrmgr_lowpower_invalid.423319979
Short name T168
Test name
Test status
Simulation time 63523618 ps
CPU time 0.7 seconds
Started Aug 06 07:49:55 PM PDT 24
Finished Aug 06 07:49:56 PM PDT 24
Peak memory 201444 kb
Host smart-e9d41cfa-6c72-4065-aff7-f8ae4a9ad887
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423319979 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_lowpower_invali
d.423319979
Directory /workspace/23.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/23.pwrmgr_reset.676393590
Short name T528
Test name
Test status
Simulation time 84952175 ps
CPU time 0.77 seconds
Started Aug 06 07:49:59 PM PDT 24
Finished Aug 06 07:50:00 PM PDT 24
Peak memory 198524 kb
Host smart-339c3e6f-cbb8-43bb-a241-d3f6cbe991f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676393590 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset.676393590
Directory /workspace/23.pwrmgr_reset/latest

Test location /workspace/coverage/default/23.pwrmgr_reset_invalid.2069330642
Short name T343
Test name
Test status
Simulation time 117073691 ps
CPU time 0.8 seconds
Started Aug 06 07:49:55 PM PDT 24
Finished Aug 06 07:49:56 PM PDT 24
Peak memory 209476 kb
Host smart-8176601a-2a32-4f42-8feb-7c72911f7bdc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069330642 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset_invalid.2069330642
Directory /workspace/23.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/23.pwrmgr_smoke.1721411749
Short name T533
Test name
Test status
Simulation time 97553000 ps
CPU time 0.62 seconds
Started Aug 06 07:49:50 PM PDT 24
Finished Aug 06 07:49:51 PM PDT 24
Peak memory 198532 kb
Host smart-132bdb6b-9d36-4eed-96bd-00386eb1f0ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721411749 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_smoke.1721411749
Directory /workspace/23.pwrmgr_smoke/latest

Test location /workspace/coverage/default/24.pwrmgr_disable_rom_integrity_check.2257881005
Short name T27
Test name
Test status
Simulation time 52309247 ps
CPU time 0.75 seconds
Started Aug 06 07:50:00 PM PDT 24
Finished Aug 06 07:50:01 PM PDT 24
Peak memory 197748 kb
Host smart-9cbb864f-71c5-40a7-afdd-43b2e6cccd18
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257881005 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_dis
able_rom_integrity_check.2257881005
Directory /workspace/24.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/24.pwrmgr_esc_clk_rst_malfunc.4061823198
Short name T461
Test name
Test status
Simulation time 28424251 ps
CPU time 0.63 seconds
Started Aug 06 07:50:00 PM PDT 24
Finished Aug 06 07:50:01 PM PDT 24
Peak memory 198072 kb
Host smart-e3aad581-ce20-40e5-ad3f-94998a5e4740
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061823198 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_esc_clk_rst
_malfunc.4061823198
Directory /workspace/24.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/24.pwrmgr_escalation_timeout.48429133
Short name T440
Test name
Test status
Simulation time 1013631389 ps
CPU time 1 seconds
Started Aug 06 07:50:01 PM PDT 24
Finished Aug 06 07:50:02 PM PDT 24
Peak memory 198112 kb
Host smart-747c29af-c099-4980-bcd6-852c095c7ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48429133 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_escalation_timeout.48429133
Directory /workspace/24.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/24.pwrmgr_glitch.1678181481
Short name T465
Test name
Test status
Simulation time 42089843 ps
CPU time 0.65 seconds
Started Aug 06 07:49:59 PM PDT 24
Finished Aug 06 07:50:00 PM PDT 24
Peak memory 197376 kb
Host smart-0f1ba816-c546-4724-9962-468045a2ebc1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678181481 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_glitch.1678181481
Directory /workspace/24.pwrmgr_glitch/latest

Test location /workspace/coverage/default/24.pwrmgr_global_esc.3006659942
Short name T212
Test name
Test status
Simulation time 65560366 ps
CPU time 0.63 seconds
Started Aug 06 07:50:01 PM PDT 24
Finished Aug 06 07:50:02 PM PDT 24
Peak memory 198184 kb
Host smart-03d368f2-fe37-40ea-b269-146b9021f57b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006659942 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_global_esc.3006659942
Directory /workspace/24.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/24.pwrmgr_reset.3367991709
Short name T501
Test name
Test status
Simulation time 166431706 ps
CPU time 0.86 seconds
Started Aug 06 07:50:01 PM PDT 24
Finished Aug 06 07:50:02 PM PDT 24
Peak memory 199104 kb
Host smart-36a319a7-4cab-4131-83f8-48ae04ca36b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367991709 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset.3367991709
Directory /workspace/24.pwrmgr_reset/latest

Test location /workspace/coverage/default/24.pwrmgr_reset_invalid.1734338858
Short name T388
Test name
Test status
Simulation time 172310798 ps
CPU time 0.79 seconds
Started Aug 06 07:50:01 PM PDT 24
Finished Aug 06 07:50:02 PM PDT 24
Peak memory 209544 kb
Host smart-adcb3a55-eb05-463f-949a-1ce6ac339835
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734338858 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset_invalid.1734338858
Directory /workspace/24.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/24.pwrmgr_sec_cm_rstmgr_intersig_mubi.3689059148
Short name T290
Test name
Test status
Simulation time 98704587 ps
CPU time 0.72 seconds
Started Aug 06 07:50:03 PM PDT 24
Finished Aug 06 07:50:04 PM PDT 24
Peak memory 198088 kb
Host smart-a477b546-13a3-49aa-a9c8-a625fb7a7863
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689059148 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3689059148
Directory /workspace/24.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/24.pwrmgr_smoke.2169943006
Short name T245
Test name
Test status
Simulation time 51172664 ps
CPU time 0.62 seconds
Started Aug 06 07:49:59 PM PDT 24
Finished Aug 06 07:49:59 PM PDT 24
Peak memory 198492 kb
Host smart-8d2364d4-8d75-4e31-8630-3079b62b1f6f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169943006 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_smoke.2169943006
Directory /workspace/24.pwrmgr_smoke/latest

Test location /workspace/coverage/default/25.pwrmgr_aborted_low_power.3772611274
Short name T619
Test name
Test status
Simulation time 49607260 ps
CPU time 0.66 seconds
Started Aug 06 07:49:53 PM PDT 24
Finished Aug 06 07:49:54 PM PDT 24
Peak memory 198756 kb
Host smart-565b169f-12d0-4a89-8a23-4e8bd8bd1670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772611274 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_aborted_low_power.3772611274
Directory /workspace/25.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/25.pwrmgr_disable_rom_integrity_check.3122537567
Short name T610
Test name
Test status
Simulation time 105466307 ps
CPU time 0.65 seconds
Started Aug 06 07:50:03 PM PDT 24
Finished Aug 06 07:50:03 PM PDT 24
Peak memory 199124 kb
Host smart-e49cdc7a-a3f3-452e-989d-3c416d8b944e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122537567 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_dis
able_rom_integrity_check.3122537567
Directory /workspace/25.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/25.pwrmgr_esc_clk_rst_malfunc.4214005029
Short name T128
Test name
Test status
Simulation time 33497053 ps
CPU time 0.63 seconds
Started Aug 06 07:50:01 PM PDT 24
Finished Aug 06 07:50:02 PM PDT 24
Peak memory 198020 kb
Host smart-1536baad-eb6b-45e4-9e66-dce42a8ed4a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214005029 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_esc_clk_rst
_malfunc.4214005029
Directory /workspace/25.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/25.pwrmgr_escalation_timeout.3535166931
Short name T413
Test name
Test status
Simulation time 160723910 ps
CPU time 0.96 seconds
Started Aug 06 07:50:07 PM PDT 24
Finished Aug 06 07:50:08 PM PDT 24
Peak memory 198124 kb
Host smart-9223a59b-dcaf-4a0c-bd1d-34538db81d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535166931 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_escalation_timeout.3535166931
Directory /workspace/25.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/25.pwrmgr_glitch.3382760016
Short name T546
Test name
Test status
Simulation time 145603406 ps
CPU time 0.61 seconds
Started Aug 06 07:50:02 PM PDT 24
Finished Aug 06 07:50:03 PM PDT 24
Peak memory 198048 kb
Host smart-343f1bcd-cb54-4d08-b430-a0f14e97a7ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382760016 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_glitch.3382760016
Directory /workspace/25.pwrmgr_glitch/latest

Test location /workspace/coverage/default/25.pwrmgr_global_esc.2876554558
Short name T305
Test name
Test status
Simulation time 51280503 ps
CPU time 0.63 seconds
Started Aug 06 07:50:03 PM PDT 24
Finished Aug 06 07:50:04 PM PDT 24
Peak memory 198424 kb
Host smart-fcc93d21-c766-4365-a676-f6906d0051bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876554558 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_global_esc.2876554558
Directory /workspace/25.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/25.pwrmgr_lowpower_invalid.509201316
Short name T181
Test name
Test status
Simulation time 52619180 ps
CPU time 0.69 seconds
Started Aug 06 07:50:03 PM PDT 24
Finished Aug 06 07:50:03 PM PDT 24
Peak memory 201424 kb
Host smart-2d9d7e2c-92d9-4777-9f44-8ed2e94bca18
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509201316 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_lowpower_invali
d.509201316
Directory /workspace/25.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/25.pwrmgr_reset.1655102570
Short name T370
Test name
Test status
Simulation time 59727034 ps
CPU time 0.83 seconds
Started Aug 06 07:50:01 PM PDT 24
Finished Aug 06 07:50:02 PM PDT 24
Peak memory 198404 kb
Host smart-1328633b-ee39-479a-a94a-0ce8dc4f2daf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655102570 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset.1655102570
Directory /workspace/25.pwrmgr_reset/latest

Test location /workspace/coverage/default/25.pwrmgr_reset_invalid.2186529861
Short name T589
Test name
Test status
Simulation time 101633808 ps
CPU time 1.04 seconds
Started Aug 06 07:50:03 PM PDT 24
Finished Aug 06 07:50:04 PM PDT 24
Peak memory 209536 kb
Host smart-7e255e43-f7cd-492a-9496-fa2a3d5cc39a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186529861 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset_invalid.2186529861
Directory /workspace/25.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/25.pwrmgr_sec_cm_rstmgr_intersig_mubi.449234048
Short name T475
Test name
Test status
Simulation time 118298469 ps
CPU time 0.75 seconds
Started Aug 06 07:50:01 PM PDT 24
Finished Aug 06 07:50:02 PM PDT 24
Peak memory 198304 kb
Host smart-f7c12bdf-7c86-4c82-a81c-ddd5a0b42430
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449234048 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_cm_rstmgr_intersig_
mubi.449234048
Directory /workspace/25.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/25.pwrmgr_smoke.639712704
Short name T452
Test name
Test status
Simulation time 59346912 ps
CPU time 0.71 seconds
Started Aug 06 07:50:01 PM PDT 24
Finished Aug 06 07:50:02 PM PDT 24
Peak memory 199368 kb
Host smart-59af0c14-71e6-400a-a4bb-bc8f7ee4b948
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639712704 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_smoke.639712704
Directory /workspace/25.pwrmgr_smoke/latest

Test location /workspace/coverage/default/26.pwrmgr_disable_rom_integrity_check.2610078206
Short name T430
Test name
Test status
Simulation time 46433475 ps
CPU time 0.83 seconds
Started Aug 06 07:50:07 PM PDT 24
Finished Aug 06 07:50:08 PM PDT 24
Peak memory 199152 kb
Host smart-6f0de3a7-0c55-4e39-8b63-8e8a984b4c6d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610078206 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_dis
able_rom_integrity_check.2610078206
Directory /workspace/26.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/26.pwrmgr_esc_clk_rst_malfunc.3552115520
Short name T506
Test name
Test status
Simulation time 78671063 ps
CPU time 0.59 seconds
Started Aug 06 07:49:57 PM PDT 24
Finished Aug 06 07:49:58 PM PDT 24
Peak memory 197304 kb
Host smart-db13266a-75a7-4d0c-af06-e38f55d4cf18
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552115520 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_esc_clk_rst
_malfunc.3552115520
Directory /workspace/26.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/26.pwrmgr_escalation_timeout.3886901000
Short name T570
Test name
Test status
Simulation time 299413575 ps
CPU time 0.97 seconds
Started Aug 06 07:50:10 PM PDT 24
Finished Aug 06 07:50:11 PM PDT 24
Peak memory 198444 kb
Host smart-e852c582-0dae-4269-8828-de8740f74260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886901000 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_escalation_timeout.3886901000
Directory /workspace/26.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/26.pwrmgr_glitch.2926538375
Short name T319
Test name
Test status
Simulation time 34929641 ps
CPU time 0.67 seconds
Started Aug 06 07:50:07 PM PDT 24
Finished Aug 06 07:50:08 PM PDT 24
Peak memory 198048 kb
Host smart-d406f85d-0c96-4c71-802b-3c6fdc491af1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926538375 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_glitch.2926538375
Directory /workspace/26.pwrmgr_glitch/latest

Test location /workspace/coverage/default/26.pwrmgr_global_esc.3742127739
Short name T48
Test name
Test status
Simulation time 57788242 ps
CPU time 0.6 seconds
Started Aug 06 07:50:08 PM PDT 24
Finished Aug 06 07:50:08 PM PDT 24
Peak memory 197928 kb
Host smart-f716f4c3-99eb-49ed-b571-dd7fd403f18a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742127739 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_global_esc.3742127739
Directory /workspace/26.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/26.pwrmgr_lowpower_invalid.2840457907
Short name T353
Test name
Test status
Simulation time 91406300 ps
CPU time 0.66 seconds
Started Aug 06 07:50:04 PM PDT 24
Finished Aug 06 07:50:05 PM PDT 24
Peak memory 201440 kb
Host smart-a185683a-c3b2-4f4d-bd43-a445f6352426
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840457907 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_lowpower_inval
id.2840457907
Directory /workspace/26.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/26.pwrmgr_reset.742886042
Short name T379
Test name
Test status
Simulation time 149909179 ps
CPU time 0.82 seconds
Started Aug 06 07:50:08 PM PDT 24
Finished Aug 06 07:50:09 PM PDT 24
Peak memory 198352 kb
Host smart-8424d5fd-b82a-4918-84de-3a9a0154c750
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742886042 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset.742886042
Directory /workspace/26.pwrmgr_reset/latest

Test location /workspace/coverage/default/26.pwrmgr_reset_invalid.4091230684
Short name T468
Test name
Test status
Simulation time 117628829 ps
CPU time 0.89 seconds
Started Aug 06 07:50:04 PM PDT 24
Finished Aug 06 07:50:06 PM PDT 24
Peak memory 209544 kb
Host smart-18b224a8-aa5e-4cad-b6a3-01b4f0740732
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091230684 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset_invalid.4091230684
Directory /workspace/26.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/26.pwrmgr_sec_cm_rstmgr_intersig_mubi.4101636564
Short name T555
Test name
Test status
Simulation time 59385034 ps
CPU time 0.8 seconds
Started Aug 06 07:50:04 PM PDT 24
Finished Aug 06 07:50:05 PM PDT 24
Peak memory 198268 kb
Host smart-484ae9d3-42e8-4e45-a758-464c7e755afc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101636564 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4101636564
Directory /workspace/26.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/26.pwrmgr_smoke.3174351734
Short name T522
Test name
Test status
Simulation time 32123385 ps
CPU time 0.67 seconds
Started Aug 06 07:50:01 PM PDT 24
Finished Aug 06 07:50:02 PM PDT 24
Peak memory 199364 kb
Host smart-22221667-c98d-4685-80e7-cfda0fde12d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174351734 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_smoke.3174351734
Directory /workspace/26.pwrmgr_smoke/latest

Test location /workspace/coverage/default/27.pwrmgr_aborted_low_power.2259668265
Short name T618
Test name
Test status
Simulation time 24819247 ps
CPU time 0.74 seconds
Started Aug 06 07:49:57 PM PDT 24
Finished Aug 06 07:49:58 PM PDT 24
Peak memory 198720 kb
Host smart-db507b4c-5746-497b-ae6e-049c19f999b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259668265 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_aborted_low_power.2259668265
Directory /workspace/27.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/27.pwrmgr_disable_rom_integrity_check.48029353
Short name T166
Test name
Test status
Simulation time 270896309 ps
CPU time 0.75 seconds
Started Aug 06 07:50:02 PM PDT 24
Finished Aug 06 07:50:03 PM PDT 24
Peak memory 198276 kb
Host smart-786a670a-7f94-4add-8ce4-5e62d5352164
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48029353 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_int
egrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_disab
le_rom_integrity_check.48029353
Directory /workspace/27.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/27.pwrmgr_esc_clk_rst_malfunc.2184317071
Short name T453
Test name
Test status
Simulation time 39893750 ps
CPU time 0.63 seconds
Started Aug 06 07:49:57 PM PDT 24
Finished Aug 06 07:49:58 PM PDT 24
Peak memory 198000 kb
Host smart-7adaf376-ca10-4039-9abc-6f320d569510
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184317071 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_esc_clk_rst
_malfunc.2184317071
Directory /workspace/27.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/27.pwrmgr_escalation_timeout.2829555099
Short name T12
Test name
Test status
Simulation time 165310157 ps
CPU time 0.96 seconds
Started Aug 06 07:50:02 PM PDT 24
Finished Aug 06 07:50:03 PM PDT 24
Peak memory 198096 kb
Host smart-c0620c82-08a4-4728-a928-c930b57d91c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829555099 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_escalation_timeout.2829555099
Directory /workspace/27.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/27.pwrmgr_glitch.43799073
Short name T362
Test name
Test status
Simulation time 26178652 ps
CPU time 0.64 seconds
Started Aug 06 07:50:02 PM PDT 24
Finished Aug 06 07:50:03 PM PDT 24
Peak memory 198084 kb
Host smart-f92277bf-56fe-4611-b880-1ca75e094d08
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43799073 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_glitch.43799073
Directory /workspace/27.pwrmgr_glitch/latest

Test location /workspace/coverage/default/27.pwrmgr_global_esc.2490605397
Short name T10
Test name
Test status
Simulation time 39375732 ps
CPU time 0.62 seconds
Started Aug 06 07:49:56 PM PDT 24
Finished Aug 06 07:49:57 PM PDT 24
Peak memory 198072 kb
Host smart-0d168e10-0725-4f02-8bc6-aefeb42c3bb3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490605397 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_global_esc.2490605397
Directory /workspace/27.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/27.pwrmgr_lowpower_invalid.2753949951
Short name T178
Test name
Test status
Simulation time 41885048 ps
CPU time 0.7 seconds
Started Aug 06 07:50:01 PM PDT 24
Finished Aug 06 07:50:02 PM PDT 24
Peak memory 201228 kb
Host smart-3258eaf2-f96e-4397-8e07-eb945b879f49
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753949951 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_lowpower_inval
id.2753949951
Directory /workspace/27.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/27.pwrmgr_reset.137595013
Short name T40
Test name
Test status
Simulation time 100865090 ps
CPU time 0.84 seconds
Started Aug 06 07:50:04 PM PDT 24
Finished Aug 06 07:50:04 PM PDT 24
Peak memory 199140 kb
Host smart-f3088864-771b-4f72-ae3c-3a25eeb2ba69
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137595013 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset.137595013
Directory /workspace/27.pwrmgr_reset/latest

Test location /workspace/coverage/default/27.pwrmgr_reset_invalid.2747315895
Short name T395
Test name
Test status
Simulation time 98004195 ps
CPU time 1.06 seconds
Started Aug 06 07:50:01 PM PDT 24
Finished Aug 06 07:50:02 PM PDT 24
Peak memory 209484 kb
Host smart-5573a949-c221-44c3-8e7f-d3caf33d9602
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747315895 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset_invalid.2747315895
Directory /workspace/27.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/27.pwrmgr_sec_cm_rstmgr_intersig_mubi.1623962350
Short name T244
Test name
Test status
Simulation time 165089221 ps
CPU time 0.66 seconds
Started Aug 06 07:49:56 PM PDT 24
Finished Aug 06 07:49:57 PM PDT 24
Peak memory 198180 kb
Host smart-218c125d-d00a-4cc2-8c56-80eb5b334ff2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623962350 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1623962350
Directory /workspace/27.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/27.pwrmgr_smoke.3844515433
Short name T451
Test name
Test status
Simulation time 30515339 ps
CPU time 0.69 seconds
Started Aug 06 07:50:04 PM PDT 24
Finished Aug 06 07:50:04 PM PDT 24
Peak memory 199404 kb
Host smart-d2a97dd3-c7e6-4eae-94a5-4a68c3365303
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844515433 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_smoke.3844515433
Directory /workspace/27.pwrmgr_smoke/latest

Test location /workspace/coverage/default/28.pwrmgr_aborted_low_power.2872209084
Short name T350
Test name
Test status
Simulation time 64660866 ps
CPU time 0.72 seconds
Started Aug 06 07:50:05 PM PDT 24
Finished Aug 06 07:50:05 PM PDT 24
Peak memory 198656 kb
Host smart-d7f1095a-1655-48c4-8571-ec54adfc8a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872209084 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_aborted_low_power.2872209084
Directory /workspace/28.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/28.pwrmgr_disable_rom_integrity_check.2577183646
Short name T566
Test name
Test status
Simulation time 61111444 ps
CPU time 0.65 seconds
Started Aug 06 07:50:25 PM PDT 24
Finished Aug 06 07:50:26 PM PDT 24
Peak memory 198556 kb
Host smart-44227d4e-129a-427e-9f78-c80b690f8fe0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577183646 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_dis
able_rom_integrity_check.2577183646
Directory /workspace/28.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/28.pwrmgr_esc_clk_rst_malfunc.115289027
Short name T560
Test name
Test status
Simulation time 29345233 ps
CPU time 0.61 seconds
Started Aug 06 07:50:23 PM PDT 24
Finished Aug 06 07:50:24 PM PDT 24
Peak memory 198092 kb
Host smart-092acf2b-10a2-4ffd-bc94-22aa83e88e55
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115289027 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_esc_clk_rst_
malfunc.115289027
Directory /workspace/28.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/28.pwrmgr_escalation_timeout.2986631286
Short name T374
Test name
Test status
Simulation time 638165526 ps
CPU time 0.91 seconds
Started Aug 06 07:50:23 PM PDT 24
Finished Aug 06 07:50:24 PM PDT 24
Peak memory 198140 kb
Host smart-80522822-c92a-4ec7-a327-3cca5aacd3ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986631286 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_escalation_timeout.2986631286
Directory /workspace/28.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/28.pwrmgr_glitch.4209202598
Short name T280
Test name
Test status
Simulation time 68363615 ps
CPU time 0.61 seconds
Started Aug 06 07:50:29 PM PDT 24
Finished Aug 06 07:50:30 PM PDT 24
Peak memory 198108 kb
Host smart-ba45e4cf-8d53-420c-ad3a-f8f6f5f4f24a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209202598 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_glitch.4209202598
Directory /workspace/28.pwrmgr_glitch/latest

Test location /workspace/coverage/default/28.pwrmgr_global_esc.2869123704
Short name T267
Test name
Test status
Simulation time 208883435 ps
CPU time 0.62 seconds
Started Aug 06 07:50:22 PM PDT 24
Finished Aug 06 07:50:23 PM PDT 24
Peak memory 198128 kb
Host smart-cea4d7ed-afea-4aac-a1c8-04004aa24746
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869123704 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_global_esc.2869123704
Directory /workspace/28.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/28.pwrmgr_lowpower_invalid.1677502252
Short name T199
Test name
Test status
Simulation time 80621544 ps
CPU time 0.69 seconds
Started Aug 06 07:50:26 PM PDT 24
Finished Aug 06 07:50:27 PM PDT 24
Peak memory 201424 kb
Host smart-d752e687-4d03-4ff6-a9ca-9747e51e92e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677502252 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_lowpower_inval
id.1677502252
Directory /workspace/28.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/28.pwrmgr_reset.1389910101
Short name T439
Test name
Test status
Simulation time 54960250 ps
CPU time 0.82 seconds
Started Aug 06 07:50:02 PM PDT 24
Finished Aug 06 07:50:03 PM PDT 24
Peak memory 198368 kb
Host smart-4e23d8ca-cf61-4457-9467-c3cd0802ac79
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389910101 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset.1389910101
Directory /workspace/28.pwrmgr_reset/latest

Test location /workspace/coverage/default/28.pwrmgr_reset_invalid.1982276447
Short name T482
Test name
Test status
Simulation time 88061696 ps
CPU time 0.85 seconds
Started Aug 06 07:50:24 PM PDT 24
Finished Aug 06 07:50:25 PM PDT 24
Peak memory 209560 kb
Host smart-4f3cfd2d-cd8e-4094-b504-7bb55dba08cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982276447 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset_invalid.1982276447
Directory /workspace/28.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/28.pwrmgr_sec_cm_rstmgr_intersig_mubi.4089775662
Short name T226
Test name
Test status
Simulation time 66752649 ps
CPU time 0.8 seconds
Started Aug 06 07:50:26 PM PDT 24
Finished Aug 06 07:50:27 PM PDT 24
Peak memory 199200 kb
Host smart-3c296fe2-8d50-48b1-abbd-83aa38c9d95e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089775662 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4089775662
Directory /workspace/28.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/28.pwrmgr_smoke.446652335
Short name T545
Test name
Test status
Simulation time 33628793 ps
CPU time 0.66 seconds
Started Aug 06 07:50:01 PM PDT 24
Finished Aug 06 07:50:02 PM PDT 24
Peak memory 198496 kb
Host smart-de120f23-b141-4d7f-87de-6c230fa3ae1d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446652335 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_smoke.446652335
Directory /workspace/28.pwrmgr_smoke/latest

Test location /workspace/coverage/default/29.pwrmgr_aborted_low_power.2882530508
Short name T105
Test name
Test status
Simulation time 95997528 ps
CPU time 0.79 seconds
Started Aug 06 07:50:24 PM PDT 24
Finished Aug 06 07:50:25 PM PDT 24
Peak memory 200160 kb
Host smart-de074fe2-9ca3-43c7-997d-092d198622e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882530508 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_aborted_low_power.2882530508
Directory /workspace/29.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/29.pwrmgr_disable_rom_integrity_check.4091222784
Short name T436
Test name
Test status
Simulation time 62601444 ps
CPU time 0.69 seconds
Started Aug 06 07:50:24 PM PDT 24
Finished Aug 06 07:50:24 PM PDT 24
Peak memory 199132 kb
Host smart-40e4a305-3ff8-43cd-9147-dcb0c1bbd3fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091222784 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_dis
able_rom_integrity_check.4091222784
Directory /workspace/29.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/29.pwrmgr_esc_clk_rst_malfunc.174383303
Short name T547
Test name
Test status
Simulation time 40612617 ps
CPU time 0.59 seconds
Started Aug 06 07:50:25 PM PDT 24
Finished Aug 06 07:50:25 PM PDT 24
Peak memory 198048 kb
Host smart-06864e80-9be8-45a3-b79e-133915fe4088
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174383303 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_esc_clk_rst_
malfunc.174383303
Directory /workspace/29.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/29.pwrmgr_escalation_timeout.388229224
Short name T609
Test name
Test status
Simulation time 606058954 ps
CPU time 0.93 seconds
Started Aug 06 07:50:24 PM PDT 24
Finished Aug 06 07:50:25 PM PDT 24
Peak memory 198120 kb
Host smart-0a53ee9b-6af8-425c-af26-f32166cdb13a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388229224 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_escalation_timeout.388229224
Directory /workspace/29.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/29.pwrmgr_glitch.3228175829
Short name T251
Test name
Test status
Simulation time 45607450 ps
CPU time 0.65 seconds
Started Aug 06 07:50:25 PM PDT 24
Finished Aug 06 07:50:26 PM PDT 24
Peak memory 198176 kb
Host smart-8b82be57-3510-474d-a76e-8abe968eb821
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228175829 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_glitch.3228175829
Directory /workspace/29.pwrmgr_glitch/latest

Test location /workspace/coverage/default/29.pwrmgr_global_esc.4011844881
Short name T264
Test name
Test status
Simulation time 33103370 ps
CPU time 0.64 seconds
Started Aug 06 07:50:29 PM PDT 24
Finished Aug 06 07:50:30 PM PDT 24
Peak memory 198380 kb
Host smart-b5bbad02-5704-4a9f-97c5-a33c20a89fdf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011844881 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_global_esc.4011844881
Directory /workspace/29.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/29.pwrmgr_lowpower_invalid.949843894
Short name T185
Test name
Test status
Simulation time 46563805 ps
CPU time 0.7 seconds
Started Aug 06 07:50:23 PM PDT 24
Finished Aug 06 07:50:24 PM PDT 24
Peak memory 201460 kb
Host smart-d6d74531-8135-451d-b9f6-95e688296abd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949843894 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_lowpower_invali
d.949843894
Directory /workspace/29.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/29.pwrmgr_reset.1320091545
Short name T483
Test name
Test status
Simulation time 73874559 ps
CPU time 0.93 seconds
Started Aug 06 07:50:25 PM PDT 24
Finished Aug 06 07:50:26 PM PDT 24
Peak memory 199180 kb
Host smart-c57fef63-721b-43bb-aeeb-aab6b9245d0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320091545 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset.1320091545
Directory /workspace/29.pwrmgr_reset/latest

Test location /workspace/coverage/default/29.pwrmgr_reset_invalid.3687787175
Short name T420
Test name
Test status
Simulation time 118261220 ps
CPU time 0.79 seconds
Started Aug 06 07:50:22 PM PDT 24
Finished Aug 06 07:50:23 PM PDT 24
Peak memory 209564 kb
Host smart-29fe9c12-c641-4141-ab40-c6978443953a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687787175 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset_invalid.3687787175
Directory /workspace/29.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/29.pwrmgr_sec_cm_rstmgr_intersig_mubi.175095031
Short name T478
Test name
Test status
Simulation time 51824735 ps
CPU time 0.93 seconds
Started Aug 06 07:50:24 PM PDT 24
Finished Aug 06 07:50:25 PM PDT 24
Peak memory 199376 kb
Host smart-58f15b03-563e-472e-9be6-9f22eb7d300a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175095031 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_cm_rstmgr_intersig_
mubi.175095031
Directory /workspace/29.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/29.pwrmgr_smoke.1762474217
Short name T455
Test name
Test status
Simulation time 31040904 ps
CPU time 0.68 seconds
Started Aug 06 07:50:23 PM PDT 24
Finished Aug 06 07:50:23 PM PDT 24
Peak memory 198532 kb
Host smart-5b2d8e32-a983-42a1-93e9-9ebc42b07f8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762474217 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_smoke.1762474217
Directory /workspace/29.pwrmgr_smoke/latest

Test location /workspace/coverage/default/3.pwrmgr_aborted_low_power.2337936408
Short name T373
Test name
Test status
Simulation time 50399415 ps
CPU time 0.57 seconds
Started Aug 06 07:48:43 PM PDT 24
Finished Aug 06 07:48:44 PM PDT 24
Peak memory 198572 kb
Host smart-1c957dfd-caff-44ca-ba9e-e2d252d08e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337936408 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_aborted_low_power.2337936408
Directory /workspace/3.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/3.pwrmgr_esc_clk_rst_malfunc.1609828869
Short name T337
Test name
Test status
Simulation time 45027022 ps
CPU time 0.61 seconds
Started Aug 06 07:48:43 PM PDT 24
Finished Aug 06 07:48:44 PM PDT 24
Peak memory 197324 kb
Host smart-8a83187c-9c73-43c1-a747-e2c11420f627
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609828869 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_esc_clk_rst_
malfunc.1609828869
Directory /workspace/3.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/3.pwrmgr_escalation_timeout.144148661
Short name T490
Test name
Test status
Simulation time 629392438 ps
CPU time 1.01 seconds
Started Aug 06 07:48:44 PM PDT 24
Finished Aug 06 07:48:45 PM PDT 24
Peak memory 198440 kb
Host smart-fdf4e8f7-1e6c-4a23-9bb0-f1d10fef4e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144148661 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_escalation_timeout.144148661
Directory /workspace/3.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/3.pwrmgr_glitch.31766023
Short name T564
Test name
Test status
Simulation time 61688571 ps
CPU time 0.61 seconds
Started Aug 06 07:48:44 PM PDT 24
Finished Aug 06 07:48:45 PM PDT 24
Peak memory 198044 kb
Host smart-7b5adc08-dc4c-4c68-bb7a-d2e3b0127b28
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31766023 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_glitch.31766023
Directory /workspace/3.pwrmgr_glitch/latest

Test location /workspace/coverage/default/3.pwrmgr_global_esc.1050017603
Short name T535
Test name
Test status
Simulation time 39458925 ps
CPU time 0.59 seconds
Started Aug 06 07:48:42 PM PDT 24
Finished Aug 06 07:48:42 PM PDT 24
Peak memory 198084 kb
Host smart-b06e8b68-9577-4554-bdbc-998caab80367
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050017603 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_global_esc.1050017603
Directory /workspace/3.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/3.pwrmgr_reset.3440664096
Short name T401
Test name
Test status
Simulation time 69326086 ps
CPU time 0.68 seconds
Started Aug 06 07:48:31 PM PDT 24
Finished Aug 06 07:48:32 PM PDT 24
Peak memory 199116 kb
Host smart-48a7840e-872d-412e-95e7-48421a16ecc6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440664096 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset.3440664096
Directory /workspace/3.pwrmgr_reset/latest

Test location /workspace/coverage/default/3.pwrmgr_reset_invalid.3740569856
Short name T437
Test name
Test status
Simulation time 172056108 ps
CPU time 0.83 seconds
Started Aug 06 07:48:45 PM PDT 24
Finished Aug 06 07:48:45 PM PDT 24
Peak memory 209608 kb
Host smart-b84622af-8a6a-4caf-bf0e-a18ed943bd85
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740569856 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset_invalid.3740569856
Directory /workspace/3.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm.513111007
Short name T30
Test name
Test status
Simulation time 386346610 ps
CPU time 1.15 seconds
Started Aug 06 07:48:54 PM PDT 24
Finished Aug 06 07:48:56 PM PDT 24
Peak memory 217540 kb
Host smart-288977a4-04b8-47be-bd6d-b4bd9f9f4d74
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513111007 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm.513111007
Directory /workspace/3.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm_rstmgr_intersig_mubi.835261940
Short name T31
Test name
Test status
Simulation time 52105945 ps
CPU time 0.78 seconds
Started Aug 06 07:48:43 PM PDT 24
Finished Aug 06 07:48:44 PM PDT 24
Peak memory 198064 kb
Host smart-d0dea90e-9df1-4a31-9bba-aaf0c1e5036f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835261940 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.835261940
Directory /workspace/3.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/3.pwrmgr_smoke.3753075329
Short name T567
Test name
Test status
Simulation time 31358475 ps
CPU time 0.68 seconds
Started Aug 06 07:48:36 PM PDT 24
Finished Aug 06 07:48:37 PM PDT 24
Peak memory 198928 kb
Host smart-df581a87-2b1c-486e-870f-e0886da6c3c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753075329 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_smoke.3753075329
Directory /workspace/3.pwrmgr_smoke/latest

Test location /workspace/coverage/default/30.pwrmgr_aborted_low_power.1089691076
Short name T498
Test name
Test status
Simulation time 37182397 ps
CPU time 0.87 seconds
Started Aug 06 07:50:27 PM PDT 24
Finished Aug 06 07:50:28 PM PDT 24
Peak memory 199216 kb
Host smart-18d4dd45-1574-4621-895f-25eb0fe47615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089691076 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_aborted_low_power.1089691076
Directory /workspace/30.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/30.pwrmgr_disable_rom_integrity_check.1260451398
Short name T450
Test name
Test status
Simulation time 50769549 ps
CPU time 0.71 seconds
Started Aug 06 07:50:26 PM PDT 24
Finished Aug 06 07:50:27 PM PDT 24
Peak memory 198168 kb
Host smart-c8880770-507c-4606-b056-d31808d8503d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260451398 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_dis
able_rom_integrity_check.1260451398
Directory /workspace/30.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/30.pwrmgr_esc_clk_rst_malfunc.1922165691
Short name T530
Test name
Test status
Simulation time 40705543 ps
CPU time 0.64 seconds
Started Aug 06 07:50:25 PM PDT 24
Finished Aug 06 07:50:26 PM PDT 24
Peak memory 198044 kb
Host smart-177c3f21-1843-4f1d-979a-694ce09ba6f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922165691 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_esc_clk_rst
_malfunc.1922165691
Directory /workspace/30.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/30.pwrmgr_escalation_timeout.3102407787
Short name T127
Test name
Test status
Simulation time 167405104 ps
CPU time 1.04 seconds
Started Aug 06 07:50:29 PM PDT 24
Finished Aug 06 07:50:30 PM PDT 24
Peak memory 198100 kb
Host smart-3aadc95b-d0ab-4072-a125-e9492236e251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102407787 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_escalation_timeout.3102407787
Directory /workspace/30.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/30.pwrmgr_glitch.588889688
Short name T584
Test name
Test status
Simulation time 45113808 ps
CPU time 0.59 seconds
Started Aug 06 07:50:27 PM PDT 24
Finished Aug 06 07:50:27 PM PDT 24
Peak memory 198028 kb
Host smart-bb72f132-ac20-463f-aea4-1ab30321e4dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588889688 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_glitch.588889688
Directory /workspace/30.pwrmgr_glitch/latest

Test location /workspace/coverage/default/30.pwrmgr_global_esc.1244944212
Short name T49
Test name
Test status
Simulation time 47219128 ps
CPU time 0.66 seconds
Started Aug 06 07:50:27 PM PDT 24
Finished Aug 06 07:50:28 PM PDT 24
Peak memory 198116 kb
Host smart-464b2ff6-971a-480c-8799-7e27562d95b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244944212 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_global_esc.1244944212
Directory /workspace/30.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/30.pwrmgr_lowpower_invalid.733898154
Short name T182
Test name
Test status
Simulation time 53919683 ps
CPU time 0.66 seconds
Started Aug 06 07:50:26 PM PDT 24
Finished Aug 06 07:50:26 PM PDT 24
Peak memory 201404 kb
Host smart-cd977d9b-d61b-4a33-8ae1-231da8f55be3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733898154 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_lowpower_invali
d.733898154
Directory /workspace/30.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/30.pwrmgr_reset.3612133781
Short name T294
Test name
Test status
Simulation time 29668390 ps
CPU time 0.7 seconds
Started Aug 06 07:50:26 PM PDT 24
Finished Aug 06 07:50:27 PM PDT 24
Peak memory 199156 kb
Host smart-7ed722e1-a19b-4689-8f49-34a92f97c91a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612133781 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset.3612133781
Directory /workspace/30.pwrmgr_reset/latest

Test location /workspace/coverage/default/30.pwrmgr_reset_invalid.2359451433
Short name T472
Test name
Test status
Simulation time 162651847 ps
CPU time 0.85 seconds
Started Aug 06 07:50:26 PM PDT 24
Finished Aug 06 07:50:27 PM PDT 24
Peak memory 209620 kb
Host smart-79210418-051a-4980-b651-3381e2e53892
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359451433 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset_invalid.2359451433
Directory /workspace/30.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/30.pwrmgr_sec_cm_rstmgr_intersig_mubi.2572826408
Short name T3
Test name
Test status
Simulation time 105288636 ps
CPU time 0.69 seconds
Started Aug 06 07:50:25 PM PDT 24
Finished Aug 06 07:50:26 PM PDT 24
Peak memory 198344 kb
Host smart-b6478dda-bd4c-466b-9fce-3af663e932bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572826408 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2572826408
Directory /workspace/30.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/30.pwrmgr_smoke.3148569096
Short name T587
Test name
Test status
Simulation time 26580457 ps
CPU time 0.69 seconds
Started Aug 06 07:50:26 PM PDT 24
Finished Aug 06 07:50:27 PM PDT 24
Peak memory 198484 kb
Host smart-a223fe40-359e-40ac-9f88-e5a6be73e162
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148569096 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_smoke.3148569096
Directory /workspace/30.pwrmgr_smoke/latest

Test location /workspace/coverage/default/31.pwrmgr_aborted_low_power.1704795399
Short name T393
Test name
Test status
Simulation time 113219893 ps
CPU time 0.88 seconds
Started Aug 06 07:50:26 PM PDT 24
Finished Aug 06 07:50:27 PM PDT 24
Peak memory 199988 kb
Host smart-01f0e1d3-edcb-4733-a8e8-2b8a35532a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704795399 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_aborted_low_power.1704795399
Directory /workspace/31.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/31.pwrmgr_disable_rom_integrity_check.1735878324
Short name T467
Test name
Test status
Simulation time 59413861 ps
CPU time 0.66 seconds
Started Aug 06 07:50:27 PM PDT 24
Finished Aug 06 07:50:27 PM PDT 24
Peak memory 198208 kb
Host smart-0ec8eb35-cc6f-4958-9534-46008986c08d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735878324 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_dis
able_rom_integrity_check.1735878324
Directory /workspace/31.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/31.pwrmgr_esc_clk_rst_malfunc.3250576644
Short name T129
Test name
Test status
Simulation time 58279516 ps
CPU time 0.6 seconds
Started Aug 06 07:50:28 PM PDT 24
Finished Aug 06 07:50:29 PM PDT 24
Peak memory 198084 kb
Host smart-16a20ed8-5f67-4967-87f7-388445a8c016
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250576644 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_esc_clk_rst
_malfunc.3250576644
Directory /workspace/31.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/31.pwrmgr_escalation_timeout.1483616679
Short name T421
Test name
Test status
Simulation time 228782580 ps
CPU time 0.93 seconds
Started Aug 06 07:50:25 PM PDT 24
Finished Aug 06 07:50:26 PM PDT 24
Peak memory 197952 kb
Host smart-f59d3341-2640-4726-97f0-d84b30dce93f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483616679 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_escalation_timeout.1483616679
Directory /workspace/31.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/31.pwrmgr_glitch.1745749489
Short name T324
Test name
Test status
Simulation time 38048684 ps
CPU time 0.68 seconds
Started Aug 06 07:50:28 PM PDT 24
Finished Aug 06 07:50:29 PM PDT 24
Peak memory 198068 kb
Host smart-b693c363-0ae6-4899-926d-a4848884e220
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745749489 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_glitch.1745749489
Directory /workspace/31.pwrmgr_glitch/latest

Test location /workspace/coverage/default/31.pwrmgr_global_esc.871921143
Short name T234
Test name
Test status
Simulation time 42763535 ps
CPU time 0.61 seconds
Started Aug 06 07:50:28 PM PDT 24
Finished Aug 06 07:50:29 PM PDT 24
Peak memory 198116 kb
Host smart-89a331cb-8fed-4ef3-9a8d-9067c6266d06
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871921143 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_global_esc.871921143
Directory /workspace/31.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/31.pwrmgr_lowpower_invalid.383730694
Short name T174
Test name
Test status
Simulation time 51118460 ps
CPU time 0.72 seconds
Started Aug 06 07:50:27 PM PDT 24
Finished Aug 06 07:50:28 PM PDT 24
Peak memory 201404 kb
Host smart-37a9a9c0-68c0-4f10-b773-8873ae2fc267
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383730694 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_lowpower_invali
d.383730694
Directory /workspace/31.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/31.pwrmgr_reset.3548767046
Short name T43
Test name
Test status
Simulation time 137098481 ps
CPU time 0.76 seconds
Started Aug 06 07:50:23 PM PDT 24
Finished Aug 06 07:50:24 PM PDT 24
Peak memory 198476 kb
Host smart-17f7906e-2e21-4c5b-b976-03ac9cc965c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548767046 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset.3548767046
Directory /workspace/31.pwrmgr_reset/latest

Test location /workspace/coverage/default/31.pwrmgr_reset_invalid.4197132034
Short name T529
Test name
Test status
Simulation time 101176093 ps
CPU time 0.93 seconds
Started Aug 06 07:50:26 PM PDT 24
Finished Aug 06 07:50:27 PM PDT 24
Peak memory 209524 kb
Host smart-3cc1bd1b-13ab-4616-bb7b-2bb5e4f4f58d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197132034 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset_invalid.4197132034
Directory /workspace/31.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/31.pwrmgr_sec_cm_rstmgr_intersig_mubi.3208156136
Short name T34
Test name
Test status
Simulation time 97182256 ps
CPU time 0.81 seconds
Started Aug 06 07:50:26 PM PDT 24
Finished Aug 06 07:50:27 PM PDT 24
Peak memory 199104 kb
Host smart-0b4d396e-d494-483a-97c3-c0205a5d529c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208156136 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3208156136
Directory /workspace/31.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/31.pwrmgr_smoke.662996767
Short name T549
Test name
Test status
Simulation time 29844370 ps
CPU time 0.67 seconds
Started Aug 06 07:50:26 PM PDT 24
Finished Aug 06 07:50:27 PM PDT 24
Peak memory 198524 kb
Host smart-63af941b-94c6-4349-a415-b1cd2195b675
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662996767 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_smoke.662996767
Directory /workspace/31.pwrmgr_smoke/latest

Test location /workspace/coverage/default/32.pwrmgr_aborted_low_power.2622819178
Short name T487
Test name
Test status
Simulation time 21731235 ps
CPU time 0.77 seconds
Started Aug 06 07:50:27 PM PDT 24
Finished Aug 06 07:50:28 PM PDT 24
Peak memory 199208 kb
Host smart-902d21a4-a685-4c6a-852a-929436c329f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622819178 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_aborted_low_power.2622819178
Directory /workspace/32.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/32.pwrmgr_disable_rom_integrity_check.3106681578
Short name T44
Test name
Test status
Simulation time 79603144 ps
CPU time 0.66 seconds
Started Aug 06 07:50:41 PM PDT 24
Finished Aug 06 07:50:42 PM PDT 24
Peak memory 198448 kb
Host smart-6b3828b0-bea7-413f-a553-bfa7b51f03c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106681578 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_dis
able_rom_integrity_check.3106681578
Directory /workspace/32.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/32.pwrmgr_esc_clk_rst_malfunc.928252554
Short name T614
Test name
Test status
Simulation time 103029261 ps
CPU time 0.57 seconds
Started Aug 06 07:50:41 PM PDT 24
Finished Aug 06 07:50:42 PM PDT 24
Peak memory 197348 kb
Host smart-a844f615-ded2-4738-9b49-18104c293ac1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928252554 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_esc_clk_rst_
malfunc.928252554
Directory /workspace/32.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/32.pwrmgr_escalation_timeout.3538515076
Short name T369
Test name
Test status
Simulation time 167796227 ps
CPU time 1.01 seconds
Started Aug 06 07:50:39 PM PDT 24
Finished Aug 06 07:50:40 PM PDT 24
Peak memory 198080 kb
Host smart-297f33d2-b05a-44a6-9904-b73619bc1969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538515076 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_escalation_timeout.3538515076
Directory /workspace/32.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/32.pwrmgr_glitch.3517967901
Short name T625
Test name
Test status
Simulation time 39638568 ps
CPU time 0.61 seconds
Started Aug 06 07:50:37 PM PDT 24
Finished Aug 06 07:50:37 PM PDT 24
Peak memory 198104 kb
Host smart-a9ce86ee-3349-41e4-b10f-d1f83b88cc77
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517967901 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_glitch.3517967901
Directory /workspace/32.pwrmgr_glitch/latest

Test location /workspace/coverage/default/32.pwrmgr_global_esc.813600899
Short name T495
Test name
Test status
Simulation time 28783181 ps
CPU time 0.61 seconds
Started Aug 06 07:50:44 PM PDT 24
Finished Aug 06 07:50:45 PM PDT 24
Peak memory 198112 kb
Host smart-2db1c7a0-b77d-4593-b083-8364b89a1ecf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813600899 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_global_esc.813600899
Directory /workspace/32.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/32.pwrmgr_lowpower_invalid.3472409832
Short name T519
Test name
Test status
Simulation time 60053033 ps
CPU time 0.68 seconds
Started Aug 06 07:50:44 PM PDT 24
Finished Aug 06 07:50:45 PM PDT 24
Peak memory 201424 kb
Host smart-e530b978-9c12-477d-9892-4b502af675cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472409832 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_lowpower_inval
id.3472409832
Directory /workspace/32.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/32.pwrmgr_reset.579797168
Short name T205
Test name
Test status
Simulation time 65071115 ps
CPU time 0.74 seconds
Started Aug 06 07:50:26 PM PDT 24
Finished Aug 06 07:50:27 PM PDT 24
Peak memory 199180 kb
Host smart-b68d59f0-ad7c-4526-a41e-c62552aa39c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579797168 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset.579797168
Directory /workspace/32.pwrmgr_reset/latest

Test location /workspace/coverage/default/32.pwrmgr_reset_invalid.839410231
Short name T239
Test name
Test status
Simulation time 158621197 ps
CPU time 0.89 seconds
Started Aug 06 07:50:41 PM PDT 24
Finished Aug 06 07:50:42 PM PDT 24
Peak memory 209572 kb
Host smart-09588ddb-4cd7-489c-a14d-e0e9edb2e944
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839410231 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset_invalid.839410231
Directory /workspace/32.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/32.pwrmgr_sec_cm_rstmgr_intersig_mubi.105705711
Short name T613
Test name
Test status
Simulation time 96266431 ps
CPU time 0.71 seconds
Started Aug 06 07:50:41 PM PDT 24
Finished Aug 06 07:50:41 PM PDT 24
Peak memory 198188 kb
Host smart-1247dafe-8f01-42c3-81c3-40c02dc55aec
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105705711 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_rstmgr_intersig_
mubi.105705711
Directory /workspace/32.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/32.pwrmgr_smoke.3473137579
Short name T95
Test name
Test status
Simulation time 38063233 ps
CPU time 0.64 seconds
Started Aug 06 07:50:28 PM PDT 24
Finished Aug 06 07:50:29 PM PDT 24
Peak memory 199324 kb
Host smart-57882757-6c8d-4c2c-8740-c6ead57d237e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473137579 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_smoke.3473137579
Directory /workspace/32.pwrmgr_smoke/latest

Test location /workspace/coverage/default/33.pwrmgr_aborted_low_power.1592073614
Short name T532
Test name
Test status
Simulation time 39448691 ps
CPU time 0.68 seconds
Started Aug 06 07:50:42 PM PDT 24
Finished Aug 06 07:50:43 PM PDT 24
Peak memory 198632 kb
Host smart-0c320366-ca3c-4517-8845-f5a212e68f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592073614 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_aborted_low_power.1592073614
Directory /workspace/33.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/33.pwrmgr_disable_rom_integrity_check.1832033720
Short name T608
Test name
Test status
Simulation time 65645440 ps
CPU time 0.69 seconds
Started Aug 06 07:50:41 PM PDT 24
Finished Aug 06 07:50:42 PM PDT 24
Peak memory 199112 kb
Host smart-ce2bae64-9e81-486f-ae5c-02c1467529e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832033720 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_dis
able_rom_integrity_check.1832033720
Directory /workspace/33.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/33.pwrmgr_esc_clk_rst_malfunc.3485936047
Short name T593
Test name
Test status
Simulation time 29827748 ps
CPU time 0.63 seconds
Started Aug 06 07:50:41 PM PDT 24
Finished Aug 06 07:50:41 PM PDT 24
Peak memory 198012 kb
Host smart-043c50ff-76aa-45db-9161-5cd5ec37501f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485936047 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_esc_clk_rst
_malfunc.3485936047
Directory /workspace/33.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/33.pwrmgr_escalation_timeout.918394715
Short name T266
Test name
Test status
Simulation time 309642180 ps
CPU time 0.97 seconds
Started Aug 06 07:50:39 PM PDT 24
Finished Aug 06 07:50:40 PM PDT 24
Peak memory 198388 kb
Host smart-a89b4c55-c0c6-40a4-b9cc-04b148284714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918394715 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_escalation_timeout.918394715
Directory /workspace/33.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/33.pwrmgr_glitch.3652483600
Short name T237
Test name
Test status
Simulation time 41438405 ps
CPU time 0.63 seconds
Started Aug 06 07:50:42 PM PDT 24
Finished Aug 06 07:50:43 PM PDT 24
Peak memory 198140 kb
Host smart-5d912f1a-ab02-49e5-a46b-b49cf8577ddb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652483600 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_glitch.3652483600
Directory /workspace/33.pwrmgr_glitch/latest

Test location /workspace/coverage/default/33.pwrmgr_global_esc.1262963842
Short name T497
Test name
Test status
Simulation time 87379214 ps
CPU time 0.59 seconds
Started Aug 06 07:50:33 PM PDT 24
Finished Aug 06 07:50:34 PM PDT 24
Peak memory 198076 kb
Host smart-35065cde-6af7-4053-9ad5-2b7cae1aae3d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262963842 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_global_esc.1262963842
Directory /workspace/33.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/33.pwrmgr_reset.2697878382
Short name T412
Test name
Test status
Simulation time 38403533 ps
CPU time 0.76 seconds
Started Aug 06 07:50:44 PM PDT 24
Finished Aug 06 07:50:45 PM PDT 24
Peak memory 199064 kb
Host smart-ca5bb160-ac10-4a02-bfcb-12b6a0db3f01
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697878382 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset.2697878382
Directory /workspace/33.pwrmgr_reset/latest

Test location /workspace/coverage/default/33.pwrmgr_reset_invalid.258954844
Short name T293
Test name
Test status
Simulation time 113962741 ps
CPU time 0.8 seconds
Started Aug 06 07:50:41 PM PDT 24
Finished Aug 06 07:50:42 PM PDT 24
Peak memory 209472 kb
Host smart-b7b7a2e1-14a0-420a-a70e-91e5dd3e0653
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258954844 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset_invalid.258954844
Directory /workspace/33.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/33.pwrmgr_sec_cm_rstmgr_intersig_mubi.2398874641
Short name T203
Test name
Test status
Simulation time 80129432 ps
CPU time 0.8 seconds
Started Aug 06 07:50:40 PM PDT 24
Finished Aug 06 07:50:41 PM PDT 24
Peak memory 198328 kb
Host smart-2624dc1c-b1d9-4521-9e06-0df342f22b4c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398874641 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2398874641
Directory /workspace/33.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/33.pwrmgr_smoke.301863354
Short name T539
Test name
Test status
Simulation time 51605170 ps
CPU time 0.6 seconds
Started Aug 06 07:50:38 PM PDT 24
Finished Aug 06 07:50:38 PM PDT 24
Peak memory 198484 kb
Host smart-e604ea7d-da75-4be9-836e-3586b47948e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301863354 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_smoke.301863354
Directory /workspace/33.pwrmgr_smoke/latest

Test location /workspace/coverage/default/34.pwrmgr_aborted_low_power.504924614
Short name T372
Test name
Test status
Simulation time 19575838 ps
CPU time 0.64 seconds
Started Aug 06 07:50:39 PM PDT 24
Finished Aug 06 07:50:40 PM PDT 24
Peak memory 198572 kb
Host smart-ec172257-1647-4567-a493-a2bf84100fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504924614 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_aborted_low_power.504924614
Directory /workspace/34.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/34.pwrmgr_disable_rom_integrity_check.1723177466
Short name T429
Test name
Test status
Simulation time 64544430 ps
CPU time 0.71 seconds
Started Aug 06 07:50:42 PM PDT 24
Finished Aug 06 07:50:44 PM PDT 24
Peak memory 198512 kb
Host smart-fceb85cf-855e-418b-bcb3-969fe57ca2d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723177466 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_dis
able_rom_integrity_check.1723177466
Directory /workspace/34.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/34.pwrmgr_esc_clk_rst_malfunc.2826277252
Short name T600
Test name
Test status
Simulation time 29729265 ps
CPU time 0.61 seconds
Started Aug 06 07:50:42 PM PDT 24
Finished Aug 06 07:50:44 PM PDT 24
Peak memory 197988 kb
Host smart-2ee8e20d-0b39-4114-a132-9fcca26d931c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826277252 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_esc_clk_rst
_malfunc.2826277252
Directory /workspace/34.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/34.pwrmgr_escalation_timeout.1811382116
Short name T558
Test name
Test status
Simulation time 165714213 ps
CPU time 1.02 seconds
Started Aug 06 07:50:39 PM PDT 24
Finished Aug 06 07:50:40 PM PDT 24
Peak memory 198088 kb
Host smart-2e7be8d0-3d90-454a-95a2-4917bd8ae78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811382116 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_escalation_timeout.1811382116
Directory /workspace/34.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/34.pwrmgr_glitch.2479674427
Short name T392
Test name
Test status
Simulation time 38117264 ps
CPU time 0.64 seconds
Started Aug 06 07:50:41 PM PDT 24
Finished Aug 06 07:50:42 PM PDT 24
Peak memory 197380 kb
Host smart-dd062e7c-2c38-47ab-8048-167f32c6cee3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479674427 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_glitch.2479674427
Directory /workspace/34.pwrmgr_glitch/latest

Test location /workspace/coverage/default/34.pwrmgr_global_esc.873374419
Short name T404
Test name
Test status
Simulation time 37569411 ps
CPU time 0.66 seconds
Started Aug 06 07:50:39 PM PDT 24
Finished Aug 06 07:50:40 PM PDT 24
Peak memory 198124 kb
Host smart-d7ba5cae-be2a-4875-9d62-98f02742492d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873374419 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_global_esc.873374419
Directory /workspace/34.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/34.pwrmgr_lowpower_invalid.2538746530
Short name T196
Test name
Test status
Simulation time 54834838 ps
CPU time 0.72 seconds
Started Aug 06 07:50:39 PM PDT 24
Finished Aug 06 07:50:40 PM PDT 24
Peak memory 201368 kb
Host smart-79b0d773-8834-4eb5-8e9c-4830209dcbcb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538746530 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_lowpower_inval
id.2538746530
Directory /workspace/34.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/34.pwrmgr_reset.1243189125
Short name T318
Test name
Test status
Simulation time 78461545 ps
CPU time 0.71 seconds
Started Aug 06 07:50:44 PM PDT 24
Finished Aug 06 07:50:45 PM PDT 24
Peak memory 198276 kb
Host smart-bad3ff01-542f-4da0-b4e9-3ccb5c2c9ba4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243189125 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset.1243189125
Directory /workspace/34.pwrmgr_reset/latest

Test location /workspace/coverage/default/34.pwrmgr_reset_invalid.2327618399
Short name T282
Test name
Test status
Simulation time 166116526 ps
CPU time 0.77 seconds
Started Aug 06 07:50:40 PM PDT 24
Finished Aug 06 07:50:40 PM PDT 24
Peak memory 209524 kb
Host smart-58ca5e65-1d61-4085-8778-21822bbf8394
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327618399 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset_invalid.2327618399
Directory /workspace/34.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/34.pwrmgr_sec_cm_ctrl_config_regwen.3854870753
Short name T56
Test name
Test status
Simulation time 54650246 ps
CPU time 0.63 seconds
Started Aug 06 07:50:39 PM PDT 24
Finished Aug 06 07:50:40 PM PDT 24
Peak memory 198524 kb
Host smart-0375edc2-cc29-40c4-aa7b-9c451be36622
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854870753 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_
cm_ctrl_config_regwen.3854870753
Directory /workspace/34.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/34.pwrmgr_sec_cm_rstmgr_intersig_mubi.2421935881
Short name T409
Test name
Test status
Simulation time 63953415 ps
CPU time 0.88 seconds
Started Aug 06 07:50:46 PM PDT 24
Finished Aug 06 07:50:47 PM PDT 24
Peak memory 199340 kb
Host smart-31ff2bbf-d8c2-4598-bf73-c9dd276309d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421935881 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2421935881
Directory /workspace/34.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/34.pwrmgr_smoke.3287122315
Short name T471
Test name
Test status
Simulation time 30335508 ps
CPU time 0.73 seconds
Started Aug 06 07:50:38 PM PDT 24
Finished Aug 06 07:50:39 PM PDT 24
Peak memory 198476 kb
Host smart-7e73344a-faac-405a-88f1-8328ce8fb1cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287122315 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_smoke.3287122315
Directory /workspace/34.pwrmgr_smoke/latest

Test location /workspace/coverage/default/35.pwrmgr_aborted_low_power.1545297311
Short name T356
Test name
Test status
Simulation time 44641605 ps
CPU time 0.94 seconds
Started Aug 06 07:50:39 PM PDT 24
Finished Aug 06 07:50:40 PM PDT 24
Peak memory 200732 kb
Host smart-6ac363d9-b29b-480a-9ff2-e55ad2d5b673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545297311 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_aborted_low_power.1545297311
Directory /workspace/35.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/35.pwrmgr_disable_rom_integrity_check.2046874551
Short name T427
Test name
Test status
Simulation time 57194618 ps
CPU time 0.73 seconds
Started Aug 06 07:50:42 PM PDT 24
Finished Aug 06 07:50:43 PM PDT 24
Peak memory 199164 kb
Host smart-3c68eeab-6d6b-4129-b494-ac9a259c08b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046874551 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_dis
able_rom_integrity_check.2046874551
Directory /workspace/35.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/35.pwrmgr_esc_clk_rst_malfunc.3037158141
Short name T216
Test name
Test status
Simulation time 36599971 ps
CPU time 0.59 seconds
Started Aug 06 07:50:36 PM PDT 24
Finished Aug 06 07:50:37 PM PDT 24
Peak memory 198048 kb
Host smart-11f374f4-73cf-4283-bfa8-1bfd837cad12
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037158141 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_esc_clk_rst
_malfunc.3037158141
Directory /workspace/35.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/35.pwrmgr_escalation_timeout.1745088824
Short name T571
Test name
Test status
Simulation time 165370355 ps
CPU time 1.02 seconds
Started Aug 06 07:50:40 PM PDT 24
Finished Aug 06 07:50:42 PM PDT 24
Peak memory 198444 kb
Host smart-03aa95b3-ec52-4e01-be64-b70e3b8b9e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745088824 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_escalation_timeout.1745088824
Directory /workspace/35.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/35.pwrmgr_glitch.1405646239
Short name T616
Test name
Test status
Simulation time 114297747 ps
CPU time 0.58 seconds
Started Aug 06 07:50:43 PM PDT 24
Finished Aug 06 07:50:44 PM PDT 24
Peak memory 198040 kb
Host smart-30ef17b6-52bb-4e9c-9a4a-52ad8a2a15c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405646239 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_glitch.1405646239
Directory /workspace/35.pwrmgr_glitch/latest

Test location /workspace/coverage/default/35.pwrmgr_global_esc.608377715
Short name T330
Test name
Test status
Simulation time 74904023 ps
CPU time 0.62 seconds
Started Aug 06 07:50:39 PM PDT 24
Finished Aug 06 07:50:40 PM PDT 24
Peak memory 198088 kb
Host smart-331441b2-116a-4706-a56a-c1077ca6cac1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608377715 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_global_esc.608377715
Directory /workspace/35.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/35.pwrmgr_reset.843494693
Short name T249
Test name
Test status
Simulation time 48090457 ps
CPU time 0.67 seconds
Started Aug 06 07:50:43 PM PDT 24
Finished Aug 06 07:50:44 PM PDT 24
Peak memory 199096 kb
Host smart-fccd2d6b-e296-456b-b0d6-f26ffbdadcdc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843494693 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset.843494693
Directory /workspace/35.pwrmgr_reset/latest

Test location /workspace/coverage/default/35.pwrmgr_reset_invalid.1429654281
Short name T527
Test name
Test status
Simulation time 110227300 ps
CPU time 1.21 seconds
Started Aug 06 07:50:42 PM PDT 24
Finished Aug 06 07:50:43 PM PDT 24
Peak memory 209516 kb
Host smart-ae3b2f22-5613-4517-9536-92dde7802123
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429654281 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset_invalid.1429654281
Directory /workspace/35.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/35.pwrmgr_sec_cm_rstmgr_intersig_mubi.58638918
Short name T312
Test name
Test status
Simulation time 50044746 ps
CPU time 0.73 seconds
Started Aug 06 07:50:42 PM PDT 24
Finished Aug 06 07:50:43 PM PDT 24
Peak memory 198096 kb
Host smart-475d5780-34fd-4101-90f3-b19e6e8c1f52
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58638918 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.58638918
Directory /workspace/35.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/35.pwrmgr_smoke.2028403381
Short name T531
Test name
Test status
Simulation time 37750671 ps
CPU time 0.63 seconds
Started Aug 06 07:50:46 PM PDT 24
Finished Aug 06 07:50:47 PM PDT 24
Peak memory 198560 kb
Host smart-f1b29ded-3576-46f4-aa6a-13ccc8e28370
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028403381 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_smoke.2028403381
Directory /workspace/35.pwrmgr_smoke/latest

Test location /workspace/coverage/default/36.pwrmgr_disable_rom_integrity_check.1992145279
Short name T538
Test name
Test status
Simulation time 71501047 ps
CPU time 0.68 seconds
Started Aug 06 07:50:43 PM PDT 24
Finished Aug 06 07:50:44 PM PDT 24
Peak memory 198296 kb
Host smart-37cd0504-f845-4b74-b25f-77f5d276a4eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992145279 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_dis
able_rom_integrity_check.1992145279
Directory /workspace/36.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/36.pwrmgr_esc_clk_rst_malfunc.3450875642
Short name T598
Test name
Test status
Simulation time 37401481 ps
CPU time 0.61 seconds
Started Aug 06 07:50:44 PM PDT 24
Finished Aug 06 07:50:45 PM PDT 24
Peak memory 197256 kb
Host smart-d13d7981-b00c-4e11-8def-de371bbc53b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450875642 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_esc_clk_rst
_malfunc.3450875642
Directory /workspace/36.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/36.pwrmgr_escalation_timeout.36853591
Short name T433
Test name
Test status
Simulation time 634794655 ps
CPU time 0.96 seconds
Started Aug 06 07:50:44 PM PDT 24
Finished Aug 06 07:50:45 PM PDT 24
Peak memory 198292 kb
Host smart-bc49f0b8-2658-4c8f-902d-2308c1e51708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36853591 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_escalation_timeout.36853591
Directory /workspace/36.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/36.pwrmgr_glitch.205627939
Short name T358
Test name
Test status
Simulation time 47108550 ps
CPU time 0.66 seconds
Started Aug 06 07:50:43 PM PDT 24
Finished Aug 06 07:50:45 PM PDT 24
Peak memory 198036 kb
Host smart-bff7a9ca-3f6b-43c9-bec5-465bfb73454e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205627939 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_glitch.205627939
Directory /workspace/36.pwrmgr_glitch/latest

Test location /workspace/coverage/default/36.pwrmgr_global_esc.2675180692
Short name T327
Test name
Test status
Simulation time 61151775 ps
CPU time 0.64 seconds
Started Aug 06 07:50:42 PM PDT 24
Finished Aug 06 07:50:44 PM PDT 24
Peak memory 198092 kb
Host smart-11a15848-0520-4e09-b2ba-181d65e79be8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675180692 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_global_esc.2675180692
Directory /workspace/36.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/36.pwrmgr_lowpower_invalid.2044887332
Short name T50
Test name
Test status
Simulation time 203455430 ps
CPU time 0.67 seconds
Started Aug 06 07:50:44 PM PDT 24
Finished Aug 06 07:50:45 PM PDT 24
Peak memory 201436 kb
Host smart-7f508908-8fa7-479e-8137-6d6990159f59
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044887332 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_lowpower_inval
id.2044887332
Directory /workspace/36.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/36.pwrmgr_reset.2132314361
Short name T448
Test name
Test status
Simulation time 79250830 ps
CPU time 0.63 seconds
Started Aug 06 07:50:42 PM PDT 24
Finished Aug 06 07:50:43 PM PDT 24
Peak memory 198272 kb
Host smart-65a2a2e9-f257-4e7a-a89f-334a8117ed06
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132314361 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset.2132314361
Directory /workspace/36.pwrmgr_reset/latest

Test location /workspace/coverage/default/36.pwrmgr_reset_invalid.3556548006
Short name T361
Test name
Test status
Simulation time 95175961 ps
CPU time 0.97 seconds
Started Aug 06 07:50:41 PM PDT 24
Finished Aug 06 07:50:43 PM PDT 24
Peak memory 209636 kb
Host smart-5e1338bc-e6db-4647-9eb1-3df17a4ebfdb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556548006 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset_invalid.3556548006
Directory /workspace/36.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/36.pwrmgr_sec_cm_rstmgr_intersig_mubi.2149150466
Short name T382
Test name
Test status
Simulation time 79119893 ps
CPU time 0.71 seconds
Started Aug 06 07:50:42 PM PDT 24
Finished Aug 06 07:50:43 PM PDT 24
Peak memory 198100 kb
Host smart-0af19a66-dc41-4b17-bfee-983738ef9a12
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149150466 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2149150466
Directory /workspace/36.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/36.pwrmgr_smoke.24879595
Short name T457
Test name
Test status
Simulation time 125854696 ps
CPU time 0.64 seconds
Started Aug 06 07:50:42 PM PDT 24
Finished Aug 06 07:50:43 PM PDT 24
Peak memory 198492 kb
Host smart-eecca4ba-6770-4856-b15f-157ad441dbce
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24879595 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_smoke.24879595
Directory /workspace/36.pwrmgr_smoke/latest

Test location /workspace/coverage/default/36.pwrmgr_wakeup.186092701
Short name T148
Test name
Test status
Simulation time 51544787 ps
CPU time 0.74 seconds
Started Aug 06 07:50:43 PM PDT 24
Finished Aug 06 07:50:45 PM PDT 24
Peak memory 198336 kb
Host smart-0c518185-5e6f-46e9-89aa-8b562661ab31
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186092701 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_wakeup.186092701
Directory /workspace/36.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/37.pwrmgr_aborted_low_power.3122670621
Short name T101
Test name
Test status
Simulation time 28543732 ps
CPU time 0.86 seconds
Started Aug 06 07:50:45 PM PDT 24
Finished Aug 06 07:50:46 PM PDT 24
Peak memory 199968 kb
Host smart-cc20159e-964e-4786-bbe6-76639ca47796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122670621 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_aborted_low_power.3122670621
Directory /workspace/37.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/37.pwrmgr_disable_rom_integrity_check.848282212
Short name T142
Test name
Test status
Simulation time 68529280 ps
CPU time 0.73 seconds
Started Aug 06 07:50:44 PM PDT 24
Finished Aug 06 07:50:45 PM PDT 24
Peak memory 199144 kb
Host smart-1d8ccc63-5e86-4114-9297-f2628e84bbb6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848282212 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_disa
ble_rom_integrity_check.848282212
Directory /workspace/37.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/37.pwrmgr_esc_clk_rst_malfunc.1569541007
Short name T263
Test name
Test status
Simulation time 30766369 ps
CPU time 0.63 seconds
Started Aug 06 07:50:44 PM PDT 24
Finished Aug 06 07:50:45 PM PDT 24
Peak memory 198048 kb
Host smart-9d602986-2731-4093-98fb-4a375d8e66f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569541007 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_esc_clk_rst
_malfunc.1569541007
Directory /workspace/37.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/37.pwrmgr_escalation_timeout.3717447236
Short name T136
Test name
Test status
Simulation time 164896544 ps
CPU time 0.94 seconds
Started Aug 06 07:50:44 PM PDT 24
Finished Aug 06 07:50:45 PM PDT 24
Peak memory 198100 kb
Host smart-d136bdf8-dcc1-4926-bb60-6bbb2ae46375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717447236 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_escalation_timeout.3717447236
Directory /workspace/37.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/37.pwrmgr_glitch.859087932
Short name T491
Test name
Test status
Simulation time 127134122 ps
CPU time 0.64 seconds
Started Aug 06 07:50:47 PM PDT 24
Finished Aug 06 07:50:48 PM PDT 24
Peak memory 198116 kb
Host smart-ed2fb100-0edd-416b-ae74-ec5cea337ec3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859087932 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_glitch.859087932
Directory /workspace/37.pwrmgr_glitch/latest

Test location /workspace/coverage/default/37.pwrmgr_global_esc.207197156
Short name T339
Test name
Test status
Simulation time 38302737 ps
CPU time 0.58 seconds
Started Aug 06 07:50:51 PM PDT 24
Finished Aug 06 07:50:52 PM PDT 24
Peak memory 198408 kb
Host smart-8697ff97-2eb7-4e9c-8d3b-ccd05996ed2e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207197156 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_global_esc.207197156
Directory /workspace/37.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/37.pwrmgr_reset.280480444
Short name T329
Test name
Test status
Simulation time 68933806 ps
CPU time 0.85 seconds
Started Aug 06 07:50:44 PM PDT 24
Finished Aug 06 07:50:46 PM PDT 24
Peak memory 198328 kb
Host smart-25c05093-4b7f-4cef-824e-096463d90a44
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280480444 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset.280480444
Directory /workspace/37.pwrmgr_reset/latest

Test location /workspace/coverage/default/37.pwrmgr_reset_invalid.2297663070
Short name T207
Test name
Test status
Simulation time 102458997 ps
CPU time 1.08 seconds
Started Aug 06 07:50:37 PM PDT 24
Finished Aug 06 07:50:38 PM PDT 24
Peak memory 209544 kb
Host smart-b87f9170-f349-4fec-be27-b3446bb44aac
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297663070 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset_invalid.2297663070
Directory /workspace/37.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/37.pwrmgr_sec_cm_rstmgr_intersig_mubi.1993124000
Short name T410
Test name
Test status
Simulation time 74233503 ps
CPU time 0.75 seconds
Started Aug 06 07:50:42 PM PDT 24
Finished Aug 06 07:50:43 PM PDT 24
Peak memory 198128 kb
Host smart-4de589df-5e5b-4851-80dd-6791d8edc981
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993124000 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1993124000
Directory /workspace/37.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/38.pwrmgr_aborted_low_power.2079274157
Short name T60
Test name
Test status
Simulation time 69426048 ps
CPU time 0.9 seconds
Started Aug 06 07:50:43 PM PDT 24
Finished Aug 06 07:50:45 PM PDT 24
Peak memory 200168 kb
Host smart-53b7f8ad-3e3b-4e9e-a3d5-6a6c75c9ee10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079274157 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_aborted_low_power.2079274157
Directory /workspace/38.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/38.pwrmgr_disable_rom_integrity_check.2745506721
Short name T492
Test name
Test status
Simulation time 64612841 ps
CPU time 0.84 seconds
Started Aug 06 07:50:41 PM PDT 24
Finished Aug 06 07:50:42 PM PDT 24
Peak memory 198500 kb
Host smart-c9db7a0d-6655-4f96-872c-576203ff9627
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745506721 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_dis
able_rom_integrity_check.2745506721
Directory /workspace/38.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/38.pwrmgr_esc_clk_rst_malfunc.170151550
Short name T36
Test name
Test status
Simulation time 28783738 ps
CPU time 0.63 seconds
Started Aug 06 07:50:41 PM PDT 24
Finished Aug 06 07:50:43 PM PDT 24
Peak memory 198012 kb
Host smart-af04e7a5-d8b3-45ea-b2f7-1f8d3d46a434
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170151550 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_esc_clk_rst_
malfunc.170151550
Directory /workspace/38.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/38.pwrmgr_escalation_timeout.1264452974
Short name T321
Test name
Test status
Simulation time 602245011 ps
CPU time 0.97 seconds
Started Aug 06 07:50:41 PM PDT 24
Finished Aug 06 07:50:42 PM PDT 24
Peak memory 198112 kb
Host smart-237d04a1-9f31-4edd-9183-dc2889a1fc70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264452974 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_escalation_timeout.1264452974
Directory /workspace/38.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/38.pwrmgr_glitch.3044353139
Short name T257
Test name
Test status
Simulation time 53849838 ps
CPU time 0.68 seconds
Started Aug 06 07:50:43 PM PDT 24
Finished Aug 06 07:50:45 PM PDT 24
Peak memory 198164 kb
Host smart-64d0eb5b-bcb5-425c-8547-938c0c20dc2f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044353139 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_glitch.3044353139
Directory /workspace/38.pwrmgr_glitch/latest

Test location /workspace/coverage/default/38.pwrmgr_global_esc.3841870345
Short name T349
Test name
Test status
Simulation time 39790634 ps
CPU time 0.58 seconds
Started Aug 06 07:50:43 PM PDT 24
Finished Aug 06 07:50:44 PM PDT 24
Peak memory 198076 kb
Host smart-35823dc0-1774-4ab7-ae80-827f860b65c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841870345 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_global_esc.3841870345
Directory /workspace/38.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/38.pwrmgr_reset.2968648600
Short name T220
Test name
Test status
Simulation time 56423513 ps
CPU time 0.78 seconds
Started Aug 06 07:50:42 PM PDT 24
Finished Aug 06 07:50:43 PM PDT 24
Peak memory 199144 kb
Host smart-6d89cda8-3d9f-4179-850f-7a8445521cc9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968648600 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset.2968648600
Directory /workspace/38.pwrmgr_reset/latest

Test location /workspace/coverage/default/38.pwrmgr_reset_invalid.3193434091
Short name T259
Test name
Test status
Simulation time 110221234 ps
CPU time 1.06 seconds
Started Aug 06 07:50:42 PM PDT 24
Finished Aug 06 07:50:44 PM PDT 24
Peak memory 209512 kb
Host smart-272dd93d-e001-490f-b099-0c85f4050b4d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193434091 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset_invalid.3193434091
Directory /workspace/38.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/38.pwrmgr_sec_cm_rstmgr_intersig_mubi.2483632909
Short name T354
Test name
Test status
Simulation time 57865621 ps
CPU time 0.8 seconds
Started Aug 06 07:50:41 PM PDT 24
Finished Aug 06 07:50:42 PM PDT 24
Peak memory 197948 kb
Host smart-aeb39d0b-1d1a-411f-82af-3a449a84df50
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483632909 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2483632909
Directory /workspace/38.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/38.pwrmgr_smoke.4074381967
Short name T230
Test name
Test status
Simulation time 26957609 ps
CPU time 0.7 seconds
Started Aug 06 07:50:42 PM PDT 24
Finished Aug 06 07:50:43 PM PDT 24
Peak memory 199256 kb
Host smart-59657db2-29df-47be-ae58-b14e18593afa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074381967 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_smoke.4074381967
Directory /workspace/38.pwrmgr_smoke/latest

Test location /workspace/coverage/default/39.pwrmgr_aborted_low_power.3613947615
Short name T365
Test name
Test status
Simulation time 70847292 ps
CPU time 0.69 seconds
Started Aug 06 07:50:42 PM PDT 24
Finished Aug 06 07:50:43 PM PDT 24
Peak memory 198780 kb
Host smart-d7c1e1fb-7209-488a-9f05-456ae4d07fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613947615 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_aborted_low_power.3613947615
Directory /workspace/39.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/39.pwrmgr_disable_rom_integrity_check.2320896654
Short name T140
Test name
Test status
Simulation time 52430519 ps
CPU time 0.78 seconds
Started Aug 06 07:50:45 PM PDT 24
Finished Aug 06 07:50:46 PM PDT 24
Peak memory 198464 kb
Host smart-d8acb83b-23e2-4d43-b8e7-0bd4ab3f18e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320896654 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_dis
able_rom_integrity_check.2320896654
Directory /workspace/39.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/39.pwrmgr_esc_clk_rst_malfunc.3137533905
Short name T274
Test name
Test status
Simulation time 33201190 ps
CPU time 0.63 seconds
Started Aug 06 07:50:44 PM PDT 24
Finished Aug 06 07:50:45 PM PDT 24
Peak memory 198044 kb
Host smart-5865177f-eaa6-4e50-8062-9d381729a666
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137533905 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_esc_clk_rst
_malfunc.3137533905
Directory /workspace/39.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/39.pwrmgr_escalation_timeout.218395506
Short name T488
Test name
Test status
Simulation time 610635694 ps
CPU time 0.97 seconds
Started Aug 06 07:50:45 PM PDT 24
Finished Aug 06 07:50:46 PM PDT 24
Peak memory 198404 kb
Host smart-91c17eee-8ee8-40b9-a078-41ca297d5d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218395506 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_escalation_timeout.218395506
Directory /workspace/39.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/39.pwrmgr_glitch.3255659349
Short name T605
Test name
Test status
Simulation time 55912338 ps
CPU time 0.72 seconds
Started Aug 06 07:50:44 PM PDT 24
Finished Aug 06 07:50:45 PM PDT 24
Peak memory 197376 kb
Host smart-cb9eefc5-8e49-4311-afc2-8984551cfd0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255659349 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_glitch.3255659349
Directory /workspace/39.pwrmgr_glitch/latest

Test location /workspace/coverage/default/39.pwrmgr_global_esc.1576927591
Short name T588
Test name
Test status
Simulation time 99503335 ps
CPU time 0.62 seconds
Started Aug 06 07:50:51 PM PDT 24
Finished Aug 06 07:50:52 PM PDT 24
Peak memory 198452 kb
Host smart-95a883d1-0eb5-44ea-8444-33bdf6f2adbd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576927591 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_global_esc.1576927591
Directory /workspace/39.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/39.pwrmgr_lowpower_invalid.4153714527
Short name T194
Test name
Test status
Simulation time 40365620 ps
CPU time 0.71 seconds
Started Aug 06 07:50:50 PM PDT 24
Finished Aug 06 07:50:51 PM PDT 24
Peak memory 201452 kb
Host smart-4dc99bf7-312f-4c71-8cee-4a4aba039e8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153714527 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_lowpower_inval
id.4153714527
Directory /workspace/39.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/39.pwrmgr_reset.1007150358
Short name T508
Test name
Test status
Simulation time 75509157 ps
CPU time 0.82 seconds
Started Aug 06 07:50:48 PM PDT 24
Finished Aug 06 07:50:49 PM PDT 24
Peak memory 199116 kb
Host smart-9ebff26e-4944-45a9-9390-2b1a4dd914c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007150358 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset.1007150358
Directory /workspace/39.pwrmgr_reset/latest

Test location /workspace/coverage/default/39.pwrmgr_reset_invalid.3917499073
Short name T41
Test name
Test status
Simulation time 111090287 ps
CPU time 0.91 seconds
Started Aug 06 07:50:45 PM PDT 24
Finished Aug 06 07:50:46 PM PDT 24
Peak memory 209472 kb
Host smart-baec81e4-7c7e-488c-9efe-e5cf946f20a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917499073 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset_invalid.3917499073
Directory /workspace/39.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/39.pwrmgr_sec_cm_rstmgr_intersig_mubi.3946039403
Short name T363
Test name
Test status
Simulation time 53154951 ps
CPU time 0.79 seconds
Started Aug 06 07:50:46 PM PDT 24
Finished Aug 06 07:50:47 PM PDT 24
Peak memory 198180 kb
Host smart-efa54304-6f16-4444-bd39-d29781d10cc4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946039403 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3946039403
Directory /workspace/39.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/39.pwrmgr_smoke.4292482212
Short name T502
Test name
Test status
Simulation time 35586643 ps
CPU time 0.64 seconds
Started Aug 06 07:50:50 PM PDT 24
Finished Aug 06 07:50:51 PM PDT 24
Peak memory 198460 kb
Host smart-9ab6f4d1-556c-4d8a-8030-13cad3e9c2b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292482212 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_smoke.4292482212
Directory /workspace/39.pwrmgr_smoke/latest

Test location /workspace/coverage/default/4.pwrmgr_aborted_low_power.3583587355
Short name T14
Test name
Test status
Simulation time 109404035 ps
CPU time 0.7 seconds
Started Aug 06 07:48:55 PM PDT 24
Finished Aug 06 07:48:56 PM PDT 24
Peak memory 198772 kb
Host smart-cf9a74b8-2c8a-4c73-ab62-5080d7dd4aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583587355 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_aborted_low_power.3583587355
Directory /workspace/4.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/4.pwrmgr_esc_clk_rst_malfunc.3654135300
Short name T553
Test name
Test status
Simulation time 44264423 ps
CPU time 0.57 seconds
Started Aug 06 07:48:53 PM PDT 24
Finished Aug 06 07:48:54 PM PDT 24
Peak memory 197344 kb
Host smart-7b87abf4-fe7e-4dd2-bdd6-c035e052d406
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654135300 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_esc_clk_rst_
malfunc.3654135300
Directory /workspace/4.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/4.pwrmgr_escalation_timeout.2006385545
Short name T258
Test name
Test status
Simulation time 524979134 ps
CPU time 0.9 seconds
Started Aug 06 07:48:56 PM PDT 24
Finished Aug 06 07:48:57 PM PDT 24
Peak memory 198100 kb
Host smart-5a4bac93-0d8c-4aaf-8bfa-d2ec52ea38df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006385545 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_escalation_timeout.2006385545
Directory /workspace/4.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/4.pwrmgr_glitch.3005999479
Short name T248
Test name
Test status
Simulation time 63984591 ps
CPU time 0.63 seconds
Started Aug 06 07:48:55 PM PDT 24
Finished Aug 06 07:48:55 PM PDT 24
Peak memory 197376 kb
Host smart-5baffe27-7b88-4fd6-902a-47b44d269d99
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005999479 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_glitch.3005999479
Directory /workspace/4.pwrmgr_glitch/latest

Test location /workspace/coverage/default/4.pwrmgr_global_esc.719326637
Short name T223
Test name
Test status
Simulation time 36185968 ps
CPU time 0.61 seconds
Started Aug 06 07:48:55 PM PDT 24
Finished Aug 06 07:48:56 PM PDT 24
Peak memory 198076 kb
Host smart-12193089-ad5f-4e3a-aeb3-61d29898646a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719326637 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_global_esc.719326637
Directory /workspace/4.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/4.pwrmgr_lowpower_invalid.1924572761
Short name T180
Test name
Test status
Simulation time 44144006 ps
CPU time 0.75 seconds
Started Aug 06 07:48:58 PM PDT 24
Finished Aug 06 07:48:59 PM PDT 24
Peak memory 201400 kb
Host smart-39287a1a-868c-4be3-8f34-7ec047e70bdd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924572761 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_lowpower_invali
d.1924572761
Directory /workspace/4.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/4.pwrmgr_reset.730173925
Short name T42
Test name
Test status
Simulation time 179650071 ps
CPU time 0.68 seconds
Started Aug 06 07:48:57 PM PDT 24
Finished Aug 06 07:48:58 PM PDT 24
Peak memory 198320 kb
Host smart-3dcb20b6-a724-46c1-81a6-c64e9ba288b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730173925 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset.730173925
Directory /workspace/4.pwrmgr_reset/latest

Test location /workspace/coverage/default/4.pwrmgr_reset_invalid.1622648067
Short name T295
Test name
Test status
Simulation time 99293874 ps
CPU time 0.87 seconds
Started Aug 06 07:48:53 PM PDT 24
Finished Aug 06 07:48:54 PM PDT 24
Peak memory 209432 kb
Host smart-2b9566dd-80e1-4cba-ad7c-21d35e85c831
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622648067 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset_invalid.1622648067
Directory /workspace/4.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm_rstmgr_intersig_mubi.1805334021
Short name T575
Test name
Test status
Simulation time 64089932 ps
CPU time 0.78 seconds
Started Aug 06 07:48:55 PM PDT 24
Finished Aug 06 07:48:56 PM PDT 24
Peak memory 199248 kb
Host smart-90496c0f-aadb-49b7-9387-a331dd6a7962
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805334021 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm_rstmgr_intersig_
mubi.1805334021
Directory /workspace/4.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/4.pwrmgr_smoke.2202780820
Short name T515
Test name
Test status
Simulation time 60206133 ps
CPU time 0.64 seconds
Started Aug 06 07:48:57 PM PDT 24
Finished Aug 06 07:48:58 PM PDT 24
Peak memory 198496 kb
Host smart-dfd77729-7e55-46b3-9b36-469e23b52aed
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202780820 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_smoke.2202780820
Directory /workspace/4.pwrmgr_smoke/latest

Test location /workspace/coverage/default/40.pwrmgr_aborted_low_power.1780343655
Short name T104
Test name
Test status
Simulation time 50042419 ps
CPU time 0.91 seconds
Started Aug 06 07:50:50 PM PDT 24
Finished Aug 06 07:50:51 PM PDT 24
Peak memory 200068 kb
Host smart-b9359f4d-957e-46ad-b7be-9775fb1ef34c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780343655 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_aborted_low_power.1780343655
Directory /workspace/40.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/40.pwrmgr_disable_rom_integrity_check.2174015794
Short name T601
Test name
Test status
Simulation time 73764475 ps
CPU time 0.64 seconds
Started Aug 06 07:50:53 PM PDT 24
Finished Aug 06 07:50:54 PM PDT 24
Peak memory 198300 kb
Host smart-30e895c6-d024-437c-9e69-12081603e629
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174015794 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_dis
able_rom_integrity_check.2174015794
Directory /workspace/40.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/40.pwrmgr_esc_clk_rst_malfunc.1837679141
Short name T594
Test name
Test status
Simulation time 38694543 ps
CPU time 0.58 seconds
Started Aug 06 07:50:56 PM PDT 24
Finished Aug 06 07:50:56 PM PDT 24
Peak memory 197324 kb
Host smart-8cc8c019-8d07-4ae7-8fbb-1607678d0ff6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837679141 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_esc_clk_rst
_malfunc.1837679141
Directory /workspace/40.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/40.pwrmgr_escalation_timeout.1996341404
Short name T270
Test name
Test status
Simulation time 160199763 ps
CPU time 0.95 seconds
Started Aug 06 07:50:53 PM PDT 24
Finished Aug 06 07:50:54 PM PDT 24
Peak memory 198128 kb
Host smart-fe00af7d-f403-4966-a033-eaf6701abf4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996341404 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_escalation_timeout.1996341404
Directory /workspace/40.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/40.pwrmgr_glitch.2546229720
Short name T405
Test name
Test status
Simulation time 50061294 ps
CPU time 0.66 seconds
Started Aug 06 07:50:43 PM PDT 24
Finished Aug 06 07:50:44 PM PDT 24
Peak memory 198048 kb
Host smart-ce47f7d4-ad65-4385-baaf-543e2051370b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546229720 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_glitch.2546229720
Directory /workspace/40.pwrmgr_glitch/latest

Test location /workspace/coverage/default/40.pwrmgr_global_esc.1986165126
Short name T211
Test name
Test status
Simulation time 37000685 ps
CPU time 0.62 seconds
Started Aug 06 07:50:46 PM PDT 24
Finished Aug 06 07:50:46 PM PDT 24
Peak memory 198132 kb
Host smart-787a5fc0-b0df-4e3d-9a0c-4b140875ed61
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986165126 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_global_esc.1986165126
Directory /workspace/40.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/40.pwrmgr_lowpower_invalid.274880430
Short name T171
Test name
Test status
Simulation time 68098643 ps
CPU time 0.67 seconds
Started Aug 06 07:50:54 PM PDT 24
Finished Aug 06 07:50:55 PM PDT 24
Peak memory 201676 kb
Host smart-019d1df4-811b-4768-bad4-ce253d39ef6b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274880430 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_lowpower_invali
d.274880430
Directory /workspace/40.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/40.pwrmgr_reset.3131545093
Short name T241
Test name
Test status
Simulation time 50802031 ps
CPU time 0.8 seconds
Started Aug 06 07:50:45 PM PDT 24
Finished Aug 06 07:50:46 PM PDT 24
Peak memory 199136 kb
Host smart-a831275b-3e3a-46e2-95c4-4e8abcef5bca
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131545093 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset.3131545093
Directory /workspace/40.pwrmgr_reset/latest

Test location /workspace/coverage/default/40.pwrmgr_reset_invalid.32593711
Short name T277
Test name
Test status
Simulation time 114321283 ps
CPU time 0.91 seconds
Started Aug 06 07:50:46 PM PDT 24
Finished Aug 06 07:50:47 PM PDT 24
Peak memory 209768 kb
Host smart-cfd16f4a-26f2-4fba-8b91-9bd04565770c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32593711 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset_invalid.32593711
Directory /workspace/40.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/40.pwrmgr_sec_cm_rstmgr_intersig_mubi.401146756
Short name T283
Test name
Test status
Simulation time 135187377 ps
CPU time 0.72 seconds
Started Aug 06 07:50:41 PM PDT 24
Finished Aug 06 07:50:42 PM PDT 24
Peak memory 198204 kb
Host smart-a242e86d-1445-4674-8ece-55137a882069
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401146756 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_cm_rstmgr_intersig_
mubi.401146756
Directory /workspace/40.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/40.pwrmgr_smoke.941596110
Short name T233
Test name
Test status
Simulation time 28941633 ps
CPU time 0.7 seconds
Started Aug 06 07:50:45 PM PDT 24
Finished Aug 06 07:50:46 PM PDT 24
Peak memory 199344 kb
Host smart-82697626-d02e-488d-88f1-0815e6346e70
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941596110 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_smoke.941596110
Directory /workspace/40.pwrmgr_smoke/latest

Test location /workspace/coverage/default/40.pwrmgr_stress_all.1302049146
Short name T629
Test name
Test status
Simulation time 109196716 ps
CPU time 0.7 seconds
Started Aug 06 07:50:44 PM PDT 24
Finished Aug 06 07:50:45 PM PDT 24
Peak memory 199156 kb
Host smart-ca368bd1-44ff-4137-8e02-23674987f760
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302049146 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_stress_all.1302049146
Directory /workspace/40.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/41.pwrmgr_aborted_low_power.486509941
Short name T302
Test name
Test status
Simulation time 33508098 ps
CPU time 0.74 seconds
Started Aug 06 07:50:43 PM PDT 24
Finished Aug 06 07:50:45 PM PDT 24
Peak memory 198832 kb
Host smart-0e19273a-f153-4a88-af69-7570470008a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486509941 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_aborted_low_power.486509941
Directory /workspace/41.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/41.pwrmgr_disable_rom_integrity_check.2864644588
Short name T470
Test name
Test status
Simulation time 58917301 ps
CPU time 0.81 seconds
Started Aug 06 07:50:42 PM PDT 24
Finished Aug 06 07:50:44 PM PDT 24
Peak memory 198556 kb
Host smart-3aa6ea00-b34f-4aeb-89ea-8dfa4f9b3ddb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864644588 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_dis
able_rom_integrity_check.2864644588
Directory /workspace/41.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/41.pwrmgr_esc_clk_rst_malfunc.1567020773
Short name T317
Test name
Test status
Simulation time 29480652 ps
CPU time 0.61 seconds
Started Aug 06 07:50:48 PM PDT 24
Finished Aug 06 07:50:49 PM PDT 24
Peak memory 198048 kb
Host smart-40332a67-cc38-4a7b-9648-a151a9967d9d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567020773 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_esc_clk_rst
_malfunc.1567020773
Directory /workspace/41.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/41.pwrmgr_escalation_timeout.395648568
Short name T332
Test name
Test status
Simulation time 315921960 ps
CPU time 0.97 seconds
Started Aug 06 07:50:46 PM PDT 24
Finished Aug 06 07:50:47 PM PDT 24
Peak memory 198116 kb
Host smart-0a841934-31f2-4c28-80ac-8916182fe787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395648568 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_escalation_timeout.395648568
Directory /workspace/41.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/41.pwrmgr_glitch.1022514663
Short name T442
Test name
Test status
Simulation time 62969607 ps
CPU time 0.6 seconds
Started Aug 06 07:50:44 PM PDT 24
Finished Aug 06 07:50:45 PM PDT 24
Peak memory 197984 kb
Host smart-85bdf409-64ee-442b-80e9-ba6cba5fc690
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022514663 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_glitch.1022514663
Directory /workspace/41.pwrmgr_glitch/latest

Test location /workspace/coverage/default/41.pwrmgr_global_esc.363144737
Short name T463
Test name
Test status
Simulation time 56142454 ps
CPU time 0.62 seconds
Started Aug 06 07:50:41 PM PDT 24
Finished Aug 06 07:50:42 PM PDT 24
Peak memory 198080 kb
Host smart-b449375c-d7ce-46b8-808e-7bc404dd1987
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363144737 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_global_esc.363144737
Directory /workspace/41.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/41.pwrmgr_lowpower_invalid.2779282069
Short name T169
Test name
Test status
Simulation time 79042966 ps
CPU time 0.71 seconds
Started Aug 06 07:50:42 PM PDT 24
Finished Aug 06 07:50:44 PM PDT 24
Peak memory 201340 kb
Host smart-1bd78d74-303b-4d5e-a551-74eb1ccf506b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779282069 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_lowpower_inval
id.2779282069
Directory /workspace/41.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/41.pwrmgr_reset.1297077612
Short name T278
Test name
Test status
Simulation time 59915165 ps
CPU time 0.88 seconds
Started Aug 06 07:50:41 PM PDT 24
Finished Aug 06 07:50:43 PM PDT 24
Peak memory 199088 kb
Host smart-a996a232-8a94-4da1-a9f2-5d4247f62e76
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297077612 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset.1297077612
Directory /workspace/41.pwrmgr_reset/latest

Test location /workspace/coverage/default/41.pwrmgr_reset_invalid.266002151
Short name T260
Test name
Test status
Simulation time 130652878 ps
CPU time 0.81 seconds
Started Aug 06 07:50:42 PM PDT 24
Finished Aug 06 07:50:43 PM PDT 24
Peak memory 209480 kb
Host smart-89162c07-23ec-46bc-a7d0-fcaa3d3794f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266002151 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset_invalid.266002151
Directory /workspace/41.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/41.pwrmgr_sec_cm_rstmgr_intersig_mubi.1070310710
Short name T289
Test name
Test status
Simulation time 50444136 ps
CPU time 0.81 seconds
Started Aug 06 07:50:43 PM PDT 24
Finished Aug 06 07:50:44 PM PDT 24
Peak memory 198188 kb
Host smart-a48d2fdf-8943-40a1-ba27-749cd2fc5f68
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070310710 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1070310710
Directory /workspace/41.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/41.pwrmgr_smoke.4071207857
Short name T360
Test name
Test status
Simulation time 60118953 ps
CPU time 0.63 seconds
Started Aug 06 07:50:43 PM PDT 24
Finished Aug 06 07:50:44 PM PDT 24
Peak memory 199412 kb
Host smart-e99be0eb-3db0-49e0-bd15-500170cb5586
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071207857 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_smoke.4071207857
Directory /workspace/41.pwrmgr_smoke/latest

Test location /workspace/coverage/default/42.pwrmgr_aborted_low_power.4002854094
Short name T466
Test name
Test status
Simulation time 33719867 ps
CPU time 0.67 seconds
Started Aug 06 07:50:42 PM PDT 24
Finished Aug 06 07:50:43 PM PDT 24
Peak memory 198776 kb
Host smart-cb46152f-1c5a-4cd6-8990-c174e84bbce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002854094 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_aborted_low_power.4002854094
Directory /workspace/42.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/42.pwrmgr_disable_rom_integrity_check.3140087049
Short name T144
Test name
Test status
Simulation time 69998492 ps
CPU time 0.65 seconds
Started Aug 06 07:51:11 PM PDT 24
Finished Aug 06 07:51:12 PM PDT 24
Peak memory 198376 kb
Host smart-bd179266-a212-4e5c-9b2e-af31e01a89e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140087049 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_dis
able_rom_integrity_check.3140087049
Directory /workspace/42.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/42.pwrmgr_esc_clk_rst_malfunc.4270712215
Short name T606
Test name
Test status
Simulation time 57456958 ps
CPU time 0.58 seconds
Started Aug 06 07:50:44 PM PDT 24
Finished Aug 06 07:50:45 PM PDT 24
Peak memory 198020 kb
Host smart-555dcfe4-2826-488f-b89a-10910d504d91
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270712215 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_esc_clk_rst
_malfunc.4270712215
Directory /workspace/42.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/42.pwrmgr_escalation_timeout.1188720645
Short name T46
Test name
Test status
Simulation time 168249735 ps
CPU time 0.98 seconds
Started Aug 06 07:50:53 PM PDT 24
Finished Aug 06 07:50:54 PM PDT 24
Peak memory 198212 kb
Host smart-cae0bce0-560f-4db0-a644-f5afe53cc796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188720645 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_escalation_timeout.1188720645
Directory /workspace/42.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/42.pwrmgr_glitch.2101981943
Short name T16
Test name
Test status
Simulation time 79322059 ps
CPU time 0.62 seconds
Started Aug 06 07:51:00 PM PDT 24
Finished Aug 06 07:51:01 PM PDT 24
Peak memory 197504 kb
Host smart-09b4ecb8-28ab-44ac-9523-6904ed6940c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101981943 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_glitch.2101981943
Directory /workspace/42.pwrmgr_glitch/latest

Test location /workspace/coverage/default/42.pwrmgr_global_esc.1795928730
Short name T389
Test name
Test status
Simulation time 87883928 ps
CPU time 0.65 seconds
Started Aug 06 07:50:42 PM PDT 24
Finished Aug 06 07:50:44 PM PDT 24
Peak memory 198072 kb
Host smart-87225ca1-ce4e-4a0a-9a1c-5c53504273eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795928730 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_global_esc.1795928730
Directory /workspace/42.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/42.pwrmgr_lowpower_invalid.621743211
Short name T97
Test name
Test status
Simulation time 304215637 ps
CPU time 0.66 seconds
Started Aug 06 07:50:51 PM PDT 24
Finished Aug 06 07:50:52 PM PDT 24
Peak memory 201372 kb
Host smart-7f0d9cf4-e27a-4890-a52b-a74d6304ff08
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621743211 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_lowpower_invali
d.621743211
Directory /workspace/42.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/42.pwrmgr_lowpower_wakeup_race.636950998
Short name T202
Test name
Test status
Simulation time 43513552 ps
CPU time 0.7 seconds
Started Aug 06 07:50:50 PM PDT 24
Finished Aug 06 07:50:51 PM PDT 24
Peak memory 198500 kb
Host smart-99bde657-f34c-4ec7-87c1-10e2eb9f3306
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636950998 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_lowpower_wa
keup_race.636950998
Directory /workspace/42.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/42.pwrmgr_reset.626414564
Short name T422
Test name
Test status
Simulation time 67799367 ps
CPU time 0.75 seconds
Started Aug 06 07:50:44 PM PDT 24
Finished Aug 06 07:50:45 PM PDT 24
Peak memory 199180 kb
Host smart-bcaeac21-5e14-42c9-9cc4-0454893782a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626414564 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset.626414564
Directory /workspace/42.pwrmgr_reset/latest

Test location /workspace/coverage/default/42.pwrmgr_reset_invalid.1926949638
Short name T579
Test name
Test status
Simulation time 264301853 ps
CPU time 0.77 seconds
Started Aug 06 07:50:53 PM PDT 24
Finished Aug 06 07:50:54 PM PDT 24
Peak memory 209508 kb
Host smart-1fc9a8be-4555-451b-ab60-636703eae855
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926949638 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset_invalid.1926949638
Directory /workspace/42.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/42.pwrmgr_sec_cm_rstmgr_intersig_mubi.1010675066
Short name T124
Test name
Test status
Simulation time 67681163 ps
CPU time 0.89 seconds
Started Aug 06 07:50:50 PM PDT 24
Finished Aug 06 07:50:51 PM PDT 24
Peak memory 199256 kb
Host smart-9acd4b83-41e7-415f-9586-7db3d16c444f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010675066 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1010675066
Directory /workspace/42.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/42.pwrmgr_smoke.2631654454
Short name T304
Test name
Test status
Simulation time 74695499 ps
CPU time 0.65 seconds
Started Aug 06 07:50:42 PM PDT 24
Finished Aug 06 07:50:43 PM PDT 24
Peak memory 198252 kb
Host smart-4007d904-faa5-4fbb-ae08-bbf706368bdf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631654454 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_smoke.2631654454
Directory /workspace/42.pwrmgr_smoke/latest

Test location /workspace/coverage/default/42.pwrmgr_wakeup.2104667091
Short name T57
Test name
Test status
Simulation time 37212688 ps
CPU time 0.66 seconds
Started Aug 06 07:50:41 PM PDT 24
Finished Aug 06 07:50:42 PM PDT 24
Peak memory 198320 kb
Host smart-8d4dd552-9a88-48a2-aac3-c05aa0052c73
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104667091 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_wakeup.2104667091
Directory /workspace/42.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/43.pwrmgr_aborted_low_power.505279300
Short name T100
Test name
Test status
Simulation time 29312138 ps
CPU time 0.63 seconds
Started Aug 06 07:51:12 PM PDT 24
Finished Aug 06 07:51:13 PM PDT 24
Peak memory 198580 kb
Host smart-30a179bf-8191-4057-8152-992fe0572718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505279300 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_aborted_low_power.505279300
Directory /workspace/43.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/43.pwrmgr_disable_rom_integrity_check.2872651794
Short name T156
Test name
Test status
Simulation time 44519395 ps
CPU time 0.7 seconds
Started Aug 06 07:50:53 PM PDT 24
Finished Aug 06 07:50:54 PM PDT 24
Peak memory 198292 kb
Host smart-781a715b-d3ed-4dc2-ac4b-d5bb46fef3aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872651794 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_dis
able_rom_integrity_check.2872651794
Directory /workspace/43.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/43.pwrmgr_esc_clk_rst_malfunc.579785384
Short name T133
Test name
Test status
Simulation time 37606622 ps
CPU time 0.59 seconds
Started Aug 06 07:51:06 PM PDT 24
Finished Aug 06 07:51:07 PM PDT 24
Peak memory 198072 kb
Host smart-8f037d4f-22e3-4093-867c-ce03e6e81f23
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579785384 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_esc_clk_rst_
malfunc.579785384
Directory /workspace/43.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/43.pwrmgr_escalation_timeout.2091432208
Short name T516
Test name
Test status
Simulation time 629630032 ps
CPU time 0.98 seconds
Started Aug 06 07:50:57 PM PDT 24
Finished Aug 06 07:50:58 PM PDT 24
Peak memory 198412 kb
Host smart-321d355a-364a-4275-ba35-16f40ea94631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091432208 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_escalation_timeout.2091432208
Directory /workspace/43.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/43.pwrmgr_glitch.794490808
Short name T456
Test name
Test status
Simulation time 53015363 ps
CPU time 0.66 seconds
Started Aug 06 07:50:53 PM PDT 24
Finished Aug 06 07:50:54 PM PDT 24
Peak memory 198116 kb
Host smart-150471cf-9c4e-49c0-a399-8a00d06ad532
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794490808 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_glitch.794490808
Directory /workspace/43.pwrmgr_glitch/latest

Test location /workspace/coverage/default/43.pwrmgr_global_esc.1746202583
Short name T415
Test name
Test status
Simulation time 24937473 ps
CPU time 0.59 seconds
Started Aug 06 07:50:50 PM PDT 24
Finished Aug 06 07:50:51 PM PDT 24
Peak memory 198428 kb
Host smart-49a21c8c-6f26-44f3-9bec-bf9b18ba54d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746202583 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_global_esc.1746202583
Directory /workspace/43.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/43.pwrmgr_lowpower_invalid.2184035187
Short name T191
Test name
Test status
Simulation time 68173334 ps
CPU time 0.74 seconds
Started Aug 06 07:51:08 PM PDT 24
Finished Aug 06 07:51:09 PM PDT 24
Peak memory 201484 kb
Host smart-f99a45c1-a559-40cf-adca-4435661d4616
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184035187 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_lowpower_inval
id.2184035187
Directory /workspace/43.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/43.pwrmgr_reset.3489045774
Short name T375
Test name
Test status
Simulation time 36661665 ps
CPU time 0.67 seconds
Started Aug 06 07:50:56 PM PDT 24
Finished Aug 06 07:50:57 PM PDT 24
Peak memory 199112 kb
Host smart-4f6e0315-63ec-43fe-b1db-8ab48e191955
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489045774 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset.3489045774
Directory /workspace/43.pwrmgr_reset/latest

Test location /workspace/coverage/default/43.pwrmgr_reset_invalid.3668318110
Short name T209
Test name
Test status
Simulation time 164592886 ps
CPU time 0.85 seconds
Started Aug 06 07:50:52 PM PDT 24
Finished Aug 06 07:50:53 PM PDT 24
Peak memory 209092 kb
Host smart-55b4dd7c-6401-4c3e-9496-cd9a25f0db66
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668318110 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset_invalid.3668318110
Directory /workspace/43.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/43.pwrmgr_sec_cm_rstmgr_intersig_mubi.2377089444
Short name T275
Test name
Test status
Simulation time 87261855 ps
CPU time 0.82 seconds
Started Aug 06 07:51:13 PM PDT 24
Finished Aug 06 07:51:14 PM PDT 24
Peak memory 198088 kb
Host smart-a2621909-fc76-47bd-993c-c5a4aea3a01a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377089444 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2377089444
Directory /workspace/43.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/43.pwrmgr_smoke.4130280822
Short name T523
Test name
Test status
Simulation time 53722908 ps
CPU time 0.63 seconds
Started Aug 06 07:50:55 PM PDT 24
Finished Aug 06 07:50:55 PM PDT 24
Peak memory 198552 kb
Host smart-c553328d-fe2a-4561-8b17-ac505e96e95b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130280822 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_smoke.4130280822
Directory /workspace/43.pwrmgr_smoke/latest

Test location /workspace/coverage/default/44.pwrmgr_aborted_low_power.2687759769
Short name T385
Test name
Test status
Simulation time 22736149 ps
CPU time 0.74 seconds
Started Aug 06 07:51:16 PM PDT 24
Finished Aug 06 07:51:16 PM PDT 24
Peak memory 199212 kb
Host smart-0e1cfb30-0384-41f1-9391-7cbc0c8c00f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687759769 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_aborted_low_power.2687759769
Directory /workspace/44.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/44.pwrmgr_disable_rom_integrity_check.2183199204
Short name T165
Test name
Test status
Simulation time 51296219 ps
CPU time 0.8 seconds
Started Aug 06 07:51:02 PM PDT 24
Finished Aug 06 07:51:02 PM PDT 24
Peak memory 199280 kb
Host smart-533f6eea-cd3f-4bb9-afc1-13e0ebb31d9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183199204 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_dis
able_rom_integrity_check.2183199204
Directory /workspace/44.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/44.pwrmgr_esc_clk_rst_malfunc.85891732
Short name T504
Test name
Test status
Simulation time 37682440 ps
CPU time 0.59 seconds
Started Aug 06 07:51:05 PM PDT 24
Finished Aug 06 07:51:06 PM PDT 24
Peak memory 198004 kb
Host smart-5006d7e3-fafe-41e5-8b08-940c106a1917
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85891732 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_mal
func_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_esc_clk_rst_m
alfunc.85891732
Directory /workspace/44.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/44.pwrmgr_escalation_timeout.3916182074
Short name T45
Test name
Test status
Simulation time 166276098 ps
CPU time 0.98 seconds
Started Aug 06 07:51:11 PM PDT 24
Finished Aug 06 07:51:12 PM PDT 24
Peak memory 198152 kb
Host smart-f40befeb-659a-4fad-8850-f0f4963473af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916182074 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_escalation_timeout.3916182074
Directory /workspace/44.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/44.pwrmgr_glitch.4136383174
Short name T525
Test name
Test status
Simulation time 54925892 ps
CPU time 0.66 seconds
Started Aug 06 07:51:05 PM PDT 24
Finished Aug 06 07:51:06 PM PDT 24
Peak memory 197332 kb
Host smart-1cb56c37-9cfd-4ae6-a74e-593e522c5227
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136383174 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_glitch.4136383174
Directory /workspace/44.pwrmgr_glitch/latest

Test location /workspace/coverage/default/44.pwrmgr_global_esc.3792951557
Short name T507
Test name
Test status
Simulation time 51150154 ps
CPU time 0.58 seconds
Started Aug 06 07:51:05 PM PDT 24
Finished Aug 06 07:51:06 PM PDT 24
Peak memory 198144 kb
Host smart-f162d7fd-0523-443c-98fe-c07fa361cdc8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792951557 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_global_esc.3792951557
Directory /workspace/44.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/44.pwrmgr_lowpower_invalid.263560003
Short name T189
Test name
Test status
Simulation time 73557352 ps
CPU time 0.66 seconds
Started Aug 06 07:50:57 PM PDT 24
Finished Aug 06 07:50:58 PM PDT 24
Peak memory 201348 kb
Host smart-9b408091-553e-4cb2-8005-73274f228e86
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263560003 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_lowpower_invali
d.263560003
Directory /workspace/44.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/44.pwrmgr_reset.2815216301
Short name T493
Test name
Test status
Simulation time 70192255 ps
CPU time 0.72 seconds
Started Aug 06 07:50:48 PM PDT 24
Finished Aug 06 07:50:49 PM PDT 24
Peak memory 199120 kb
Host smart-ff86e33c-93bf-4c61-93e6-11dec5eeb371
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815216301 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset.2815216301
Directory /workspace/44.pwrmgr_reset/latest

Test location /workspace/coverage/default/44.pwrmgr_reset_invalid.1052955122
Short name T35
Test name
Test status
Simulation time 106176681 ps
CPU time 1.06 seconds
Started Aug 06 07:51:11 PM PDT 24
Finished Aug 06 07:51:12 PM PDT 24
Peak memory 209528 kb
Host smart-2d2c8a73-f861-4ab9-954d-8c5a11237b65
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052955122 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset_invalid.1052955122
Directory /workspace/44.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/44.pwrmgr_sec_cm_rstmgr_intersig_mubi.271268481
Short name T536
Test name
Test status
Simulation time 80754471 ps
CPU time 0.79 seconds
Started Aug 06 07:50:56 PM PDT 24
Finished Aug 06 07:50:57 PM PDT 24
Peak memory 198072 kb
Host smart-72bf4f9a-d9cd-4153-9d84-2ff26296b752
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271268481 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_cm_rstmgr_intersig_
mubi.271268481
Directory /workspace/44.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/44.pwrmgr_smoke.4185415281
Short name T326
Test name
Test status
Simulation time 119260179 ps
CPU time 0.63 seconds
Started Aug 06 07:50:59 PM PDT 24
Finished Aug 06 07:51:00 PM PDT 24
Peak memory 198488 kb
Host smart-99669cc9-884d-4255-97ed-a74ed8c25f48
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185415281 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_smoke.4185415281
Directory /workspace/44.pwrmgr_smoke/latest

Test location /workspace/coverage/default/44.pwrmgr_wakeup.2458139292
Short name T551
Test name
Test status
Simulation time 26177720 ps
CPU time 0.64 seconds
Started Aug 06 07:50:56 PM PDT 24
Finished Aug 06 07:50:56 PM PDT 24
Peak memory 198252 kb
Host smart-4e9f291a-fbf8-4c5b-abd5-42315709db8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458139292 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_wakeup.2458139292
Directory /workspace/44.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/45.pwrmgr_aborted_low_power.3370036277
Short name T578
Test name
Test status
Simulation time 46732242 ps
CPU time 0.93 seconds
Started Aug 06 07:50:51 PM PDT 24
Finished Aug 06 07:50:52 PM PDT 24
Peak memory 200284 kb
Host smart-79c8368b-bc94-4f33-9a76-a9b065ab5591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370036277 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_aborted_low_power.3370036277
Directory /workspace/45.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/45.pwrmgr_disable_rom_integrity_check.4171337107
Short name T438
Test name
Test status
Simulation time 63447191 ps
CPU time 0.75 seconds
Started Aug 06 07:50:56 PM PDT 24
Finished Aug 06 07:50:57 PM PDT 24
Peak memory 198376 kb
Host smart-3cc3f5b0-e1ea-497a-9cd1-eee3a8dd8065
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171337107 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_dis
able_rom_integrity_check.4171337107
Directory /workspace/45.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/45.pwrmgr_esc_clk_rst_malfunc.3327519288
Short name T366
Test name
Test status
Simulation time 44292339 ps
CPU time 0.59 seconds
Started Aug 06 07:51:05 PM PDT 24
Finished Aug 06 07:51:05 PM PDT 24
Peak memory 198084 kb
Host smart-61fe1434-e366-4d4c-8b47-b05c95ab42f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327519288 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_esc_clk_rst
_malfunc.3327519288
Directory /workspace/45.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/45.pwrmgr_escalation_timeout.4117084253
Short name T39
Test name
Test status
Simulation time 525754137 ps
CPU time 0.96 seconds
Started Aug 06 07:50:59 PM PDT 24
Finished Aug 06 07:51:00 PM PDT 24
Peak memory 198072 kb
Host smart-3dddb029-e5df-4db2-9aa1-88835794abb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117084253 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_escalation_timeout.4117084253
Directory /workspace/45.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/45.pwrmgr_glitch.3116250515
Short name T512
Test name
Test status
Simulation time 32335856 ps
CPU time 0.65 seconds
Started Aug 06 07:50:57 PM PDT 24
Finished Aug 06 07:50:58 PM PDT 24
Peak memory 198084 kb
Host smart-a7addb5a-a9da-48ac-bb95-0502da708c8e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116250515 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_glitch.3116250515
Directory /workspace/45.pwrmgr_glitch/latest

Test location /workspace/coverage/default/45.pwrmgr_global_esc.3538532716
Short name T620
Test name
Test status
Simulation time 83217400 ps
CPU time 0.58 seconds
Started Aug 06 07:50:56 PM PDT 24
Finished Aug 06 07:50:56 PM PDT 24
Peak memory 198072 kb
Host smart-6d943014-350d-4a78-82e6-9733a0ab6892
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538532716 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_global_esc.3538532716
Directory /workspace/45.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/45.pwrmgr_reset.4264844480
Short name T574
Test name
Test status
Simulation time 284859104 ps
CPU time 0.72 seconds
Started Aug 06 07:50:52 PM PDT 24
Finished Aug 06 07:50:52 PM PDT 24
Peak memory 198412 kb
Host smart-d1610cf0-e3a6-494a-bca6-686dd320e95c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264844480 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset.4264844480
Directory /workspace/45.pwrmgr_reset/latest

Test location /workspace/coverage/default/45.pwrmgr_reset_invalid.754431562
Short name T242
Test name
Test status
Simulation time 163400519 ps
CPU time 0.8 seconds
Started Aug 06 07:50:57 PM PDT 24
Finished Aug 06 07:50:59 PM PDT 24
Peak memory 201236 kb
Host smart-2be98930-b16f-4e5f-a883-497d04bf970e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754431562 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset_invalid.754431562
Directory /workspace/45.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/45.pwrmgr_sec_cm_rstmgr_intersig_mubi.2716693589
Short name T88
Test name
Test status
Simulation time 81451137 ps
CPU time 0.69 seconds
Started Aug 06 07:50:57 PM PDT 24
Finished Aug 06 07:50:58 PM PDT 24
Peak memory 197868 kb
Host smart-507184f0-2978-4bcf-82bb-87238a0d8824
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716693589 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2716693589
Directory /workspace/45.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/45.pwrmgr_smoke.483031956
Short name T624
Test name
Test status
Simulation time 29495470 ps
CPU time 0.68 seconds
Started Aug 06 07:51:09 PM PDT 24
Finished Aug 06 07:51:10 PM PDT 24
Peak memory 198516 kb
Host smart-9693df04-6b48-4bf7-aa8a-1fbb9fd8d7fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483031956 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_smoke.483031956
Directory /workspace/45.pwrmgr_smoke/latest

Test location /workspace/coverage/default/46.pwrmgr_aborted_low_power.2986635999
Short name T414
Test name
Test status
Simulation time 35844085 ps
CPU time 0.71 seconds
Started Aug 06 07:51:18 PM PDT 24
Finished Aug 06 07:51:19 PM PDT 24
Peak memory 199192 kb
Host smart-f6836abe-e7b8-4b32-bda2-abcf60f474cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986635999 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_aborted_low_power.2986635999
Directory /workspace/46.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/46.pwrmgr_disable_rom_integrity_check.2183825711
Short name T298
Test name
Test status
Simulation time 65092629 ps
CPU time 0.79 seconds
Started Aug 06 07:51:14 PM PDT 24
Finished Aug 06 07:51:15 PM PDT 24
Peak memory 198476 kb
Host smart-dee15762-7526-43d0-958f-bde1514e3445
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183825711 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_dis
able_rom_integrity_check.2183825711
Directory /workspace/46.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/46.pwrmgr_esc_clk_rst_malfunc.533419787
Short name T434
Test name
Test status
Simulation time 38416946 ps
CPU time 0.62 seconds
Started Aug 06 07:51:09 PM PDT 24
Finished Aug 06 07:51:10 PM PDT 24
Peak memory 198040 kb
Host smart-1f1de061-1391-42f1-8c3a-8d0e92173d55
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533419787 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_esc_clk_rst_
malfunc.533419787
Directory /workspace/46.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/46.pwrmgr_escalation_timeout.2270993457
Short name T367
Test name
Test status
Simulation time 339476663 ps
CPU time 0.97 seconds
Started Aug 06 07:50:58 PM PDT 24
Finished Aug 06 07:50:59 PM PDT 24
Peak memory 198368 kb
Host smart-a1a989cd-9f28-4d57-b7ff-3e9b99fdabd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270993457 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_escalation_timeout.2270993457
Directory /workspace/46.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/46.pwrmgr_glitch.930852004
Short name T279
Test name
Test status
Simulation time 128667155 ps
CPU time 0.6 seconds
Started Aug 06 07:51:11 PM PDT 24
Finished Aug 06 07:51:12 PM PDT 24
Peak memory 198136 kb
Host smart-5562a66a-a780-47b4-b253-110efddecf8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930852004 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_glitch.930852004
Directory /workspace/46.pwrmgr_glitch/latest

Test location /workspace/coverage/default/46.pwrmgr_global_esc.3203057498
Short name T213
Test name
Test status
Simulation time 33520841 ps
CPU time 0.65 seconds
Started Aug 06 07:51:04 PM PDT 24
Finished Aug 06 07:51:05 PM PDT 24
Peak memory 198084 kb
Host smart-b301e499-9283-42d0-8d97-1918ba386b86
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203057498 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_global_esc.3203057498
Directory /workspace/46.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/46.pwrmgr_lowpower_invalid.307323077
Short name T190
Test name
Test status
Simulation time 43814866 ps
CPU time 0.67 seconds
Started Aug 06 07:51:13 PM PDT 24
Finished Aug 06 07:51:14 PM PDT 24
Peak memory 201444 kb
Host smart-37354a4f-70f8-4ec1-bf0a-d8e56a55b14c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307323077 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_lowpower_invali
d.307323077
Directory /workspace/46.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/46.pwrmgr_reset.1716351395
Short name T534
Test name
Test status
Simulation time 45955398 ps
CPU time 0.74 seconds
Started Aug 06 07:51:18 PM PDT 24
Finished Aug 06 07:51:19 PM PDT 24
Peak memory 198384 kb
Host smart-10b62240-4966-43d8-a5a3-89ac05a2e15f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716351395 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset.1716351395
Directory /workspace/46.pwrmgr_reset/latest

Test location /workspace/coverage/default/46.pwrmgr_reset_invalid.2263349790
Short name T449
Test name
Test status
Simulation time 173989375 ps
CPU time 0.83 seconds
Started Aug 06 07:51:14 PM PDT 24
Finished Aug 06 07:51:15 PM PDT 24
Peak memory 209604 kb
Host smart-4ce06c37-ab2a-47ec-b122-1d4924127fc9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263349790 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset_invalid.2263349790
Directory /workspace/46.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/46.pwrmgr_sec_cm_rstmgr_intersig_mubi.3965078911
Short name T391
Test name
Test status
Simulation time 64261519 ps
CPU time 0.88 seconds
Started Aug 06 07:50:57 PM PDT 24
Finished Aug 06 07:50:59 PM PDT 24
Peak memory 199048 kb
Host smart-f83045b6-4900-4db2-ae0f-105bec784f34
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965078911 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3965078911
Directory /workspace/46.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/46.pwrmgr_smoke.2676479545
Short name T357
Test name
Test status
Simulation time 32044144 ps
CPU time 0.68 seconds
Started Aug 06 07:50:57 PM PDT 24
Finished Aug 06 07:50:58 PM PDT 24
Peak memory 198460 kb
Host smart-afdeb9d4-704c-40af-a1ee-faceca1acee3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676479545 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_smoke.2676479545
Directory /workspace/46.pwrmgr_smoke/latest

Test location /workspace/coverage/default/47.pwrmgr_aborted_low_power.2842455094
Short name T540
Test name
Test status
Simulation time 43741892 ps
CPU time 0.65 seconds
Started Aug 06 07:51:00 PM PDT 24
Finished Aug 06 07:51:00 PM PDT 24
Peak memory 199168 kb
Host smart-d963cc5d-88aa-44dd-9134-62aec6d7e65e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842455094 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_aborted_low_power.2842455094
Directory /workspace/47.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/47.pwrmgr_disable_rom_integrity_check.3681210944
Short name T143
Test name
Test status
Simulation time 71823415 ps
CPU time 0.65 seconds
Started Aug 06 07:51:09 PM PDT 24
Finished Aug 06 07:51:09 PM PDT 24
Peak memory 198300 kb
Host smart-47c7f8f2-607e-4ea2-b7cd-182374c8ce91
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681210944 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_dis
able_rom_integrity_check.3681210944
Directory /workspace/47.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/47.pwrmgr_esc_clk_rst_malfunc.3725543792
Short name T621
Test name
Test status
Simulation time 38902068 ps
CPU time 0.56 seconds
Started Aug 06 07:51:00 PM PDT 24
Finished Aug 06 07:51:01 PM PDT 24
Peak memory 198036 kb
Host smart-1d2c605f-0644-43a3-8715-50dbf957b3ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725543792 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_esc_clk_rst
_malfunc.3725543792
Directory /workspace/47.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/47.pwrmgr_escalation_timeout.2144089546
Short name T489
Test name
Test status
Simulation time 163586941 ps
CPU time 1.03 seconds
Started Aug 06 07:51:00 PM PDT 24
Finished Aug 06 07:51:02 PM PDT 24
Peak memory 198084 kb
Host smart-1df74b6a-41f4-4717-9e5e-d652176b0130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144089546 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_escalation_timeout.2144089546
Directory /workspace/47.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/47.pwrmgr_glitch.984348266
Short name T219
Test name
Test status
Simulation time 55798347 ps
CPU time 0.57 seconds
Started Aug 06 07:50:49 PM PDT 24
Finished Aug 06 07:50:50 PM PDT 24
Peak memory 198028 kb
Host smart-1d57cd66-60a3-4f94-a593-ffa014362627
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984348266 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_glitch.984348266
Directory /workspace/47.pwrmgr_glitch/latest

Test location /workspace/coverage/default/47.pwrmgr_global_esc.225073292
Short name T550
Test name
Test status
Simulation time 23217763 ps
CPU time 0.59 seconds
Started Aug 06 07:50:59 PM PDT 24
Finished Aug 06 07:51:00 PM PDT 24
Peak memory 198084 kb
Host smart-d49ceaa0-7fd4-4d19-bf8b-24530b40c544
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225073292 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_global_esc.225073292
Directory /workspace/47.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/47.pwrmgr_lowpower_invalid.2548392445
Short name T90
Test name
Test status
Simulation time 43761085 ps
CPU time 0.74 seconds
Started Aug 06 07:51:15 PM PDT 24
Finished Aug 06 07:51:16 PM PDT 24
Peak memory 201388 kb
Host smart-7da413bd-72b5-4ba0-b449-7637054e8b8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548392445 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_lowpower_inval
id.2548392445
Directory /workspace/47.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/47.pwrmgr_reset.3852579712
Short name T554
Test name
Test status
Simulation time 74671613 ps
CPU time 0.79 seconds
Started Aug 06 07:51:00 PM PDT 24
Finished Aug 06 07:51:01 PM PDT 24
Peak memory 199164 kb
Host smart-a168d91f-b83f-4b6d-8200-f7ebe9211f8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852579712 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset.3852579712
Directory /workspace/47.pwrmgr_reset/latest

Test location /workspace/coverage/default/47.pwrmgr_reset_invalid.3889756146
Short name T417
Test name
Test status
Simulation time 98234140 ps
CPU time 0.96 seconds
Started Aug 06 07:51:17 PM PDT 24
Finished Aug 06 07:51:18 PM PDT 24
Peak memory 209572 kb
Host smart-91a12935-25af-4adf-832e-5797f23da021
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889756146 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset_invalid.3889756146
Directory /workspace/47.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/47.pwrmgr_sec_cm_rstmgr_intersig_mubi.504141064
Short name T548
Test name
Test status
Simulation time 112057186 ps
CPU time 0.76 seconds
Started Aug 06 07:51:14 PM PDT 24
Finished Aug 06 07:51:15 PM PDT 24
Peak memory 198232 kb
Host smart-efd45e1b-51c9-4634-ba4f-99dcc87e8988
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504141064 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_cm_rstmgr_intersig_
mubi.504141064
Directory /workspace/47.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/47.pwrmgr_smoke.194485610
Short name T229
Test name
Test status
Simulation time 40905680 ps
CPU time 0.7 seconds
Started Aug 06 07:51:13 PM PDT 24
Finished Aug 06 07:51:14 PM PDT 24
Peak memory 198580 kb
Host smart-2dde3147-2646-4c45-87f0-acc93f775aa3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194485610 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_smoke.194485610
Directory /workspace/47.pwrmgr_smoke/latest

Test location /workspace/coverage/default/48.pwrmgr_aborted_low_power.958551641
Short name T408
Test name
Test status
Simulation time 87384120 ps
CPU time 0.74 seconds
Started Aug 06 07:51:12 PM PDT 24
Finished Aug 06 07:51:13 PM PDT 24
Peak memory 198924 kb
Host smart-7831694a-18bd-45d2-b1ca-12a0ecc0264f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958551641 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_aborted_low_power.958551641
Directory /workspace/48.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/48.pwrmgr_disable_rom_integrity_check.1994185752
Short name T141
Test name
Test status
Simulation time 88958964 ps
CPU time 0.66 seconds
Started Aug 06 07:51:10 PM PDT 24
Finished Aug 06 07:51:11 PM PDT 24
Peak memory 198488 kb
Host smart-5746e140-5a98-4f9c-976e-6b3cc7bf1677
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994185752 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_dis
able_rom_integrity_check.1994185752
Directory /workspace/48.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/48.pwrmgr_esc_clk_rst_malfunc.676436986
Short name T311
Test name
Test status
Simulation time 29293469 ps
CPU time 0.59 seconds
Started Aug 06 07:51:15 PM PDT 24
Finished Aug 06 07:51:16 PM PDT 24
Peak memory 198072 kb
Host smart-71ba2211-7de0-4af7-ac2f-d725e6743492
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676436986 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_esc_clk_rst_
malfunc.676436986
Directory /workspace/48.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/48.pwrmgr_escalation_timeout.539906636
Short name T347
Test name
Test status
Simulation time 164302961 ps
CPU time 0.94 seconds
Started Aug 06 07:51:12 PM PDT 24
Finished Aug 06 07:51:14 PM PDT 24
Peak memory 198104 kb
Host smart-7c444de7-7e3d-4bab-aab5-add6aa0224bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539906636 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_escalation_timeout.539906636
Directory /workspace/48.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/48.pwrmgr_glitch.1967969658
Short name T494
Test name
Test status
Simulation time 51868455 ps
CPU time 0.59 seconds
Started Aug 06 07:51:15 PM PDT 24
Finished Aug 06 07:51:15 PM PDT 24
Peak memory 198024 kb
Host smart-0de9797c-ec96-4ae0-b15e-7a212a9458fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967969658 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_glitch.1967969658
Directory /workspace/48.pwrmgr_glitch/latest

Test location /workspace/coverage/default/48.pwrmgr_global_esc.4114759815
Short name T403
Test name
Test status
Simulation time 81672804 ps
CPU time 0.56 seconds
Started Aug 06 07:51:14 PM PDT 24
Finished Aug 06 07:51:15 PM PDT 24
Peak memory 198408 kb
Host smart-4782f8e1-baa0-4609-8c70-fd9690258d30
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114759815 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_global_esc.4114759815
Directory /workspace/48.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/48.pwrmgr_lowpower_invalid.3401198950
Short name T179
Test name
Test status
Simulation time 63904702 ps
CPU time 0.67 seconds
Started Aug 06 07:51:10 PM PDT 24
Finished Aug 06 07:51:11 PM PDT 24
Peak memory 201232 kb
Host smart-8b1dec4a-4189-43c6-976e-c9b016d02268
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401198950 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_lowpower_inval
id.3401198950
Directory /workspace/48.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/48.pwrmgr_reset.1330582267
Short name T247
Test name
Test status
Simulation time 103988838 ps
CPU time 0.79 seconds
Started Aug 06 07:51:09 PM PDT 24
Finished Aug 06 07:51:10 PM PDT 24
Peak memory 198252 kb
Host smart-87e34ee0-0088-4828-b761-e10ceb16eada
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330582267 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset.1330582267
Directory /workspace/48.pwrmgr_reset/latest

Test location /workspace/coverage/default/48.pwrmgr_reset_invalid.1211749568
Short name T517
Test name
Test status
Simulation time 159086264 ps
CPU time 0.85 seconds
Started Aug 06 07:51:14 PM PDT 24
Finished Aug 06 07:51:15 PM PDT 24
Peak memory 209380 kb
Host smart-086c93e7-44da-4647-8783-90401f17bc50
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211749568 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset_invalid.1211749568
Directory /workspace/48.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/48.pwrmgr_sec_cm_rstmgr_intersig_mubi.3692153970
Short name T204
Test name
Test status
Simulation time 93847009 ps
CPU time 0.9 seconds
Started Aug 06 07:51:09 PM PDT 24
Finished Aug 06 07:51:10 PM PDT 24
Peak memory 199372 kb
Host smart-f0a1125d-ec4b-4afc-8663-0d6bd3456c31
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692153970 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3692153970
Directory /workspace/48.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/48.pwrmgr_smoke.326888609
Short name T6
Test name
Test status
Simulation time 120434301 ps
CPU time 0.59 seconds
Started Aug 06 07:51:12 PM PDT 24
Finished Aug 06 07:51:13 PM PDT 24
Peak memory 198508 kb
Host smart-eee08a61-52e0-43d3-acf1-b16b8520cb15
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326888609 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_smoke.326888609
Directory /workspace/48.pwrmgr_smoke/latest

Test location /workspace/coverage/default/49.pwrmgr_aborted_low_power.2485641163
Short name T576
Test name
Test status
Simulation time 26523087 ps
CPU time 0.88 seconds
Started Aug 06 07:51:37 PM PDT 24
Finished Aug 06 07:51:38 PM PDT 24
Peak memory 199208 kb
Host smart-e27f2397-5842-4dd1-9478-02fb728d765f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485641163 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_aborted_low_power.2485641163
Directory /workspace/49.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/49.pwrmgr_disable_rom_integrity_check.580545127
Short name T364
Test name
Test status
Simulation time 81313934 ps
CPU time 0.66 seconds
Started Aug 06 07:51:18 PM PDT 24
Finished Aug 06 07:51:18 PM PDT 24
Peak memory 199200 kb
Host smart-0040978f-5693-46f7-be17-71ee3f7f03a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580545127 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_disa
ble_rom_integrity_check.580545127
Directory /workspace/49.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/49.pwrmgr_esc_clk_rst_malfunc.3618156521
Short name T135
Test name
Test status
Simulation time 29568539 ps
CPU time 0.65 seconds
Started Aug 06 07:51:20 PM PDT 24
Finished Aug 06 07:51:21 PM PDT 24
Peak memory 198040 kb
Host smart-173dc77a-b0c9-4698-881e-bcfebcbb14ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618156521 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_esc_clk_rst
_malfunc.3618156521
Directory /workspace/49.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/49.pwrmgr_escalation_timeout.489710976
Short name T285
Test name
Test status
Simulation time 161298874 ps
CPU time 1.08 seconds
Started Aug 06 07:51:20 PM PDT 24
Finished Aug 06 07:51:21 PM PDT 24
Peak memory 198140 kb
Host smart-854cb214-27ca-47a8-8671-b48c062531db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489710976 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_escalation_timeout.489710976
Directory /workspace/49.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/49.pwrmgr_glitch.2444861480
Short name T435
Test name
Test status
Simulation time 107141016 ps
CPU time 0.62 seconds
Started Aug 06 07:51:27 PM PDT 24
Finished Aug 06 07:51:28 PM PDT 24
Peak memory 198056 kb
Host smart-e0d94cc7-9c9c-4e2e-8854-b462f51a6454
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444861480 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_glitch.2444861480
Directory /workspace/49.pwrmgr_glitch/latest

Test location /workspace/coverage/default/49.pwrmgr_global_esc.1223228285
Short name T232
Test name
Test status
Simulation time 23558117 ps
CPU time 0.6 seconds
Started Aug 06 07:51:25 PM PDT 24
Finished Aug 06 07:51:26 PM PDT 24
Peak memory 198064 kb
Host smart-6b62cf83-2171-4f95-80cf-47aeffd7d931
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223228285 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_global_esc.1223228285
Directory /workspace/49.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/49.pwrmgr_lowpower_invalid.1003445403
Short name T543
Test name
Test status
Simulation time 51195124 ps
CPU time 0.65 seconds
Started Aug 06 07:51:18 PM PDT 24
Finished Aug 06 07:51:19 PM PDT 24
Peak memory 201420 kb
Host smart-a6ad9cca-890c-4846-b152-172faed243a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003445403 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_lowpower_inval
id.1003445403
Directory /workspace/49.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/49.pwrmgr_reset.326809600
Short name T335
Test name
Test status
Simulation time 35885725 ps
CPU time 0.65 seconds
Started Aug 06 07:51:16 PM PDT 24
Finished Aug 06 07:51:16 PM PDT 24
Peak memory 198168 kb
Host smart-2b5b6089-7abd-48ca-b718-d7356f2554ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326809600 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset.326809600
Directory /workspace/49.pwrmgr_reset/latest

Test location /workspace/coverage/default/49.pwrmgr_reset_invalid.765762947
Short name T542
Test name
Test status
Simulation time 109477216 ps
CPU time 1.09 seconds
Started Aug 06 07:51:24 PM PDT 24
Finished Aug 06 07:51:25 PM PDT 24
Peak memory 209468 kb
Host smart-5b958efa-6685-4187-8dce-c2549fa1713e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765762947 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset_invalid.765762947
Directory /workspace/49.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/49.pwrmgr_sec_cm_rstmgr_intersig_mubi.2746242231
Short name T628
Test name
Test status
Simulation time 79458770 ps
CPU time 0.71 seconds
Started Aug 06 07:51:18 PM PDT 24
Finished Aug 06 07:51:19 PM PDT 24
Peak memory 197932 kb
Host smart-02a09d7e-dfc6-497a-b6b9-e044e952060a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746242231 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2746242231
Directory /workspace/49.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/49.pwrmgr_smoke.2498696605
Short name T432
Test name
Test status
Simulation time 28766941 ps
CPU time 0.66 seconds
Started Aug 06 07:51:13 PM PDT 24
Finished Aug 06 07:51:14 PM PDT 24
Peak memory 199380 kb
Host smart-698def8e-64b5-4471-9ac7-3d41af56a2be
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498696605 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_smoke.2498696605
Directory /workspace/49.pwrmgr_smoke/latest

Test location /workspace/coverage/default/49.pwrmgr_wakeup.4032024480
Short name T149
Test name
Test status
Simulation time 80816465 ps
CPU time 0.64 seconds
Started Aug 06 07:51:21 PM PDT 24
Finished Aug 06 07:51:22 PM PDT 24
Peak memory 198492 kb
Host smart-da1daacc-443d-455b-9caf-a50e51f001bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032024480 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_wakeup.4032024480
Directory /workspace/49.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/5.pwrmgr_aborted_low_power.2566393811
Short name T103
Test name
Test status
Simulation time 66409599 ps
CPU time 0.79 seconds
Started Aug 06 07:48:56 PM PDT 24
Finished Aug 06 07:48:56 PM PDT 24
Peak memory 200076 kb
Host smart-cc134ba1-2284-4136-8828-2605c3c3dc93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566393811 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_aborted_low_power.2566393811
Directory /workspace/5.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/5.pwrmgr_disable_rom_integrity_check.2750628879
Short name T431
Test name
Test status
Simulation time 91365093 ps
CPU time 0.64 seconds
Started Aug 06 07:48:58 PM PDT 24
Finished Aug 06 07:48:59 PM PDT 24
Peak memory 199216 kb
Host smart-78c5b0af-7d15-4a75-8779-906630fbe80a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750628879 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_disa
ble_rom_integrity_check.2750628879
Directory /workspace/5.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/5.pwrmgr_esc_clk_rst_malfunc.1587137883
Short name T377
Test name
Test status
Simulation time 30281931 ps
CPU time 0.61 seconds
Started Aug 06 07:48:57 PM PDT 24
Finished Aug 06 07:48:57 PM PDT 24
Peak memory 197392 kb
Host smart-e8c2c543-e615-41c3-9fe8-ddcea1443b0a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587137883 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_esc_clk_rst_
malfunc.1587137883
Directory /workspace/5.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/5.pwrmgr_escalation_timeout.1389348444
Short name T376
Test name
Test status
Simulation time 160526844 ps
CPU time 0.99 seconds
Started Aug 06 07:48:57 PM PDT 24
Finished Aug 06 07:48:58 PM PDT 24
Peak memory 198116 kb
Host smart-fe4c6b1a-8856-4dd4-baca-98da336c52f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389348444 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_escalation_timeout.1389348444
Directory /workspace/5.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/5.pwrmgr_glitch.3614081564
Short name T486
Test name
Test status
Simulation time 40182859 ps
CPU time 0.63 seconds
Started Aug 06 07:48:56 PM PDT 24
Finished Aug 06 07:48:56 PM PDT 24
Peak memory 198056 kb
Host smart-1a2adf7c-96a2-4bcb-84f1-8d1bf4920952
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614081564 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_glitch.3614081564
Directory /workspace/5.pwrmgr_glitch/latest

Test location /workspace/coverage/default/5.pwrmgr_global_esc.3748959030
Short name T307
Test name
Test status
Simulation time 81814701 ps
CPU time 0.61 seconds
Started Aug 06 07:48:56 PM PDT 24
Finished Aug 06 07:48:56 PM PDT 24
Peak memory 198100 kb
Host smart-a4607b6f-0c70-4fb3-a1b4-196933a6eb9e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748959030 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_global_esc.3748959030
Directory /workspace/5.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/5.pwrmgr_lowpower_invalid.233577162
Short name T428
Test name
Test status
Simulation time 41538355 ps
CPU time 0.75 seconds
Started Aug 06 07:49:00 PM PDT 24
Finished Aug 06 07:49:00 PM PDT 24
Peak memory 201408 kb
Host smart-5c2f5241-7584-488e-b483-a3ae8cc1a44f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233577162 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_lowpower_invalid
.233577162
Directory /workspace/5.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/5.pwrmgr_reset.1589097225
Short name T224
Test name
Test status
Simulation time 175009826 ps
CPU time 0.75 seconds
Started Aug 06 07:49:01 PM PDT 24
Finished Aug 06 07:49:02 PM PDT 24
Peak memory 198464 kb
Host smart-39dfe5bc-4ae2-4de2-ac32-06853b263f19
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589097225 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset.1589097225
Directory /workspace/5.pwrmgr_reset/latest

Test location /workspace/coverage/default/5.pwrmgr_reset_invalid.2306095528
Short name T284
Test name
Test status
Simulation time 156329185 ps
CPU time 0.78 seconds
Started Aug 06 07:48:56 PM PDT 24
Finished Aug 06 07:48:57 PM PDT 24
Peak memory 209500 kb
Host smart-408c5a3f-adac-45ce-8ae4-f28bb5c57225
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306095528 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset_invalid.2306095528
Directory /workspace/5.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/5.pwrmgr_sec_cm_rstmgr_intersig_mubi.3596776159
Short name T126
Test name
Test status
Simulation time 73280114 ps
CPU time 0.92 seconds
Started Aug 06 07:48:57 PM PDT 24
Finished Aug 06 07:48:58 PM PDT 24
Peak memory 198704 kb
Host smart-ff998a5a-84f0-4fbc-a2b5-95d4308c7f97
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596776159 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm_rstmgr_intersig_
mubi.3596776159
Directory /workspace/5.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/6.pwrmgr_aborted_low_power.1816001062
Short name T333
Test name
Test status
Simulation time 87170732 ps
CPU time 0.67 seconds
Started Aug 06 07:48:57 PM PDT 24
Finished Aug 06 07:48:58 PM PDT 24
Peak memory 198740 kb
Host smart-3fb3ecf9-b398-49e1-bbc6-3d6f57dc438a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816001062 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_aborted_low_power.1816001062
Directory /workspace/6.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/6.pwrmgr_disable_rom_integrity_check.733922186
Short name T509
Test name
Test status
Simulation time 57235328 ps
CPU time 0.7 seconds
Started Aug 06 07:49:00 PM PDT 24
Finished Aug 06 07:49:00 PM PDT 24
Peak memory 199176 kb
Host smart-0fcafe94-a25a-45da-b111-f8d18f3ce630
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733922186 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_disab
le_rom_integrity_check.733922186
Directory /workspace/6.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/6.pwrmgr_esc_clk_rst_malfunc.2483412396
Short name T336
Test name
Test status
Simulation time 30217417 ps
CPU time 0.62 seconds
Started Aug 06 07:48:58 PM PDT 24
Finished Aug 06 07:48:59 PM PDT 24
Peak memory 198036 kb
Host smart-c14b3151-347c-44bb-982d-751b6f0df426
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483412396 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_esc_clk_rst_
malfunc.2483412396
Directory /workspace/6.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/6.pwrmgr_escalation_timeout.3420760910
Short name T286
Test name
Test status
Simulation time 167210314 ps
CPU time 1.08 seconds
Started Aug 06 07:49:01 PM PDT 24
Finished Aug 06 07:49:02 PM PDT 24
Peak memory 198172 kb
Host smart-01821a06-6bc5-4dd4-8fe4-75b0a23b6a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420760910 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_escalation_timeout.3420760910
Directory /workspace/6.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/6.pwrmgr_glitch.3097446173
Short name T24
Test name
Test status
Simulation time 40471437 ps
CPU time 0.64 seconds
Started Aug 06 07:48:59 PM PDT 24
Finished Aug 06 07:48:59 PM PDT 24
Peak memory 197344 kb
Host smart-55ad25e0-b656-4ae0-9a40-252ae462f9b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097446173 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_glitch.3097446173
Directory /workspace/6.pwrmgr_glitch/latest

Test location /workspace/coverage/default/6.pwrmgr_global_esc.1869398240
Short name T419
Test name
Test status
Simulation time 37199594 ps
CPU time 0.62 seconds
Started Aug 06 07:48:58 PM PDT 24
Finished Aug 06 07:48:58 PM PDT 24
Peak memory 198080 kb
Host smart-6f1f260d-f1e0-45bf-a52d-e7fa7020d506
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869398240 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_global_esc.1869398240
Directory /workspace/6.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/6.pwrmgr_lowpower_invalid.4293980708
Short name T520
Test name
Test status
Simulation time 44379744 ps
CPU time 0.79 seconds
Started Aug 06 07:48:55 PM PDT 24
Finished Aug 06 07:48:56 PM PDT 24
Peak memory 201472 kb
Host smart-e70febfc-5b0c-4b25-a666-d346f5792779
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293980708 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_lowpower_invali
d.4293980708
Directory /workspace/6.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/6.pwrmgr_reset.232372617
Short name T246
Test name
Test status
Simulation time 25410620 ps
CPU time 0.63 seconds
Started Aug 06 07:48:57 PM PDT 24
Finished Aug 06 07:48:58 PM PDT 24
Peak memory 197748 kb
Host smart-af8d945f-9d13-44c2-87c1-ea03e970ced5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232372617 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset.232372617
Directory /workspace/6.pwrmgr_reset/latest

Test location /workspace/coverage/default/6.pwrmgr_reset_invalid.3594102042
Short name T344
Test name
Test status
Simulation time 101454307 ps
CPU time 0.9 seconds
Started Aug 06 07:48:55 PM PDT 24
Finished Aug 06 07:48:56 PM PDT 24
Peak memory 209536 kb
Host smart-7bd5d3a5-7c80-4d00-afb3-9bd2e2956d9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594102042 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset_invalid.3594102042
Directory /workspace/6.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/6.pwrmgr_sec_cm_rstmgr_intersig_mubi.2112969609
Short name T236
Test name
Test status
Simulation time 62914257 ps
CPU time 0.71 seconds
Started Aug 06 07:49:00 PM PDT 24
Finished Aug 06 07:49:01 PM PDT 24
Peak memory 198180 kb
Host smart-19466217-836e-4b64-939d-dfdd6b300ce0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112969609 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2112969609
Directory /workspace/6.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/6.pwrmgr_smoke.3973125459
Short name T602
Test name
Test status
Simulation time 52931804 ps
CPU time 0.65 seconds
Started Aug 06 07:49:00 PM PDT 24
Finished Aug 06 07:49:01 PM PDT 24
Peak memory 199440 kb
Host smart-662d77f5-5449-4694-bcc3-1c3e366b67cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973125459 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_smoke.3973125459
Directory /workspace/6.pwrmgr_smoke/latest

Test location /workspace/coverage/default/7.pwrmgr_aborted_low_power.1299614021
Short name T580
Test name
Test status
Simulation time 101249286 ps
CPU time 0.79 seconds
Started Aug 06 07:48:55 PM PDT 24
Finished Aug 06 07:48:56 PM PDT 24
Peak memory 200020 kb
Host smart-fa757a43-5d40-4dd7-8de7-78d7d4df9716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299614021 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_aborted_low_power.1299614021
Directory /workspace/7.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/7.pwrmgr_disable_rom_integrity_check.1135657382
Short name T445
Test name
Test status
Simulation time 59987926 ps
CPU time 0.88 seconds
Started Aug 06 07:49:01 PM PDT 24
Finished Aug 06 07:49:02 PM PDT 24
Peak memory 198484 kb
Host smart-95afdfec-5c16-4dfe-a60f-dd841593f07e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135657382 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_disa
ble_rom_integrity_check.1135657382
Directory /workspace/7.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/7.pwrmgr_esc_clk_rst_malfunc.3408794172
Short name T416
Test name
Test status
Simulation time 34458201 ps
CPU time 0.62 seconds
Started Aug 06 07:49:00 PM PDT 24
Finished Aug 06 07:49:00 PM PDT 24
Peak memory 198092 kb
Host smart-447d530b-d874-476b-9300-82791af7ea7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408794172 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_esc_clk_rst_
malfunc.3408794172
Directory /workspace/7.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/7.pwrmgr_escalation_timeout.1459806907
Short name T222
Test name
Test status
Simulation time 1086724523 ps
CPU time 1.02 seconds
Started Aug 06 07:49:00 PM PDT 24
Finished Aug 06 07:49:01 PM PDT 24
Peak memory 198156 kb
Host smart-f7d38ab6-bdd4-485a-8c89-4edad08222ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459806907 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_escalation_timeout.1459806907
Directory /workspace/7.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/7.pwrmgr_glitch.649884865
Short name T481
Test name
Test status
Simulation time 45718045 ps
CPU time 0.66 seconds
Started Aug 06 07:49:01 PM PDT 24
Finished Aug 06 07:49:02 PM PDT 24
Peak memory 198096 kb
Host smart-ad257d9c-4966-46b7-a7dc-73f36f9b9a0c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649884865 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_glitch.649884865
Directory /workspace/7.pwrmgr_glitch/latest

Test location /workspace/coverage/default/7.pwrmgr_global_esc.290731524
Short name T511
Test name
Test status
Simulation time 33636056 ps
CPU time 0.58 seconds
Started Aug 06 07:48:59 PM PDT 24
Finished Aug 06 07:48:59 PM PDT 24
Peak memory 198116 kb
Host smart-f71c6bee-29a7-4d00-9c0a-52b918e560d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290731524 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_global_esc.290731524
Directory /workspace/7.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/7.pwrmgr_lowpower_invalid.95066007
Short name T183
Test name
Test status
Simulation time 51174744 ps
CPU time 0.75 seconds
Started Aug 06 07:49:01 PM PDT 24
Finished Aug 06 07:49:02 PM PDT 24
Peak memory 201448 kb
Host smart-b4e2dcd7-5f51-4ee4-abd8-d6b31992028c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95066007 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invali
d_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_lowpower_invalid.95066007
Directory /workspace/7.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/7.pwrmgr_reset.812069685
Short name T281
Test name
Test status
Simulation time 89822072 ps
CPU time 0.92 seconds
Started Aug 06 07:48:59 PM PDT 24
Finished Aug 06 07:49:00 PM PDT 24
Peak memory 198408 kb
Host smart-86d28f76-bd7a-4089-a6da-6a646a7ac203
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812069685 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset.812069685
Directory /workspace/7.pwrmgr_reset/latest

Test location /workspace/coverage/default/7.pwrmgr_reset_invalid.3313446091
Short name T254
Test name
Test status
Simulation time 109599955 ps
CPU time 1.16 seconds
Started Aug 06 07:49:01 PM PDT 24
Finished Aug 06 07:49:02 PM PDT 24
Peak memory 209468 kb
Host smart-c4f2e245-1cbb-4744-b157-11bf692b6791
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313446091 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset_invalid.3313446091
Directory /workspace/7.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/7.pwrmgr_sec_cm_rstmgr_intersig_mubi.456718537
Short name T473
Test name
Test status
Simulation time 64864285 ps
CPU time 0.7 seconds
Started Aug 06 07:48:55 PM PDT 24
Finished Aug 06 07:48:56 PM PDT 24
Peak memory 198064 kb
Host smart-9e687529-ce35-4cba-8f2c-70ef4215c3c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456718537 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.456718537
Directory /workspace/7.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/7.pwrmgr_smoke.2286645803
Short name T338
Test name
Test status
Simulation time 39127252 ps
CPU time 0.66 seconds
Started Aug 06 07:48:56 PM PDT 24
Finished Aug 06 07:48:57 PM PDT 24
Peak memory 199364 kb
Host smart-2f386f79-5345-46e6-a287-a30050ad72ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286645803 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_smoke.2286645803
Directory /workspace/7.pwrmgr_smoke/latest

Test location /workspace/coverage/default/8.pwrmgr_aborted_low_power.77980484
Short name T383
Test name
Test status
Simulation time 30115009 ps
CPU time 0.79 seconds
Started Aug 06 07:49:02 PM PDT 24
Finished Aug 06 07:49:02 PM PDT 24
Peak memory 198984 kb
Host smart-6bcec796-7b0a-4f71-8e5b-0d27dbab3656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77980484 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_aborted_low_power.77980484
Directory /workspace/8.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/8.pwrmgr_disable_rom_integrity_check.3344332958
Short name T446
Test name
Test status
Simulation time 55487700 ps
CPU time 0.87 seconds
Started Aug 06 07:49:01 PM PDT 24
Finished Aug 06 07:49:02 PM PDT 24
Peak memory 199104 kb
Host smart-78a3f503-9d02-48dc-90ea-bfe5aab17b89
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344332958 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_disa
ble_rom_integrity_check.3344332958
Directory /workspace/8.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.1838164872
Short name T225
Test name
Test status
Simulation time 30366380 ps
CPU time 0.7 seconds
Started Aug 06 07:49:01 PM PDT 24
Finished Aug 06 07:49:02 PM PDT 24
Peak memory 198056 kb
Host smart-55f6e9a1-330c-499b-b239-409a22a323d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838164872 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_esc_clk_rst_
malfunc.1838164872
Directory /workspace/8.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/8.pwrmgr_escalation_timeout.2886703850
Short name T325
Test name
Test status
Simulation time 166587000 ps
CPU time 1.07 seconds
Started Aug 06 07:48:59 PM PDT 24
Finished Aug 06 07:49:01 PM PDT 24
Peak memory 198436 kb
Host smart-21bac49f-b213-4e39-bee4-4c29132c33eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886703850 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_escalation_timeout.2886703850
Directory /workspace/8.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/8.pwrmgr_glitch.259966287
Short name T331
Test name
Test status
Simulation time 38239637 ps
CPU time 0.68 seconds
Started Aug 06 07:49:00 PM PDT 24
Finished Aug 06 07:49:01 PM PDT 24
Peak memory 197580 kb
Host smart-1dca1c6a-0bf4-40c9-bba6-e4c68ea0628b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259966287 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_glitch.259966287
Directory /workspace/8.pwrmgr_glitch/latest

Test location /workspace/coverage/default/8.pwrmgr_global_esc.1026952569
Short name T505
Test name
Test status
Simulation time 24644523 ps
CPU time 0.62 seconds
Started Aug 06 07:49:00 PM PDT 24
Finished Aug 06 07:49:01 PM PDT 24
Peak memory 197588 kb
Host smart-b9df5449-cca4-413e-a5e4-5435be80e1fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026952569 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_global_esc.1026952569
Directory /workspace/8.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/8.pwrmgr_lowpower_invalid.656029026
Short name T198
Test name
Test status
Simulation time 69283371 ps
CPU time 0.66 seconds
Started Aug 06 07:49:00 PM PDT 24
Finished Aug 06 07:49:01 PM PDT 24
Peak memory 201388 kb
Host smart-396c0602-6d65-48df-93aa-be6a872597f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656029026 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_lowpower_invalid
.656029026
Directory /workspace/8.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/8.pwrmgr_reset.550883807
Short name T503
Test name
Test status
Simulation time 65137050 ps
CPU time 0.69 seconds
Started Aug 06 07:49:00 PM PDT 24
Finished Aug 06 07:49:01 PM PDT 24
Peak memory 198408 kb
Host smart-9411abc6-eaa5-4129-ac8e-09c14b018de6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550883807 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset.550883807
Directory /workspace/8.pwrmgr_reset/latest

Test location /workspace/coverage/default/8.pwrmgr_reset_invalid.1864273365
Short name T447
Test name
Test status
Simulation time 134143853 ps
CPU time 0.82 seconds
Started Aug 06 07:49:00 PM PDT 24
Finished Aug 06 07:49:01 PM PDT 24
Peak memory 209484 kb
Host smart-543b2d25-a5b9-4cb1-a2be-bffef61342cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864273365 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset_invalid.1864273365
Directory /workspace/8.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.1545157771
Short name T208
Test name
Test status
Simulation time 78795338 ps
CPU time 0.85 seconds
Started Aug 06 07:49:03 PM PDT 24
Finished Aug 06 07:49:04 PM PDT 24
Peak memory 198156 kb
Host smart-473708c5-f215-4a92-b202-fea1da91b4c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545157771 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm_rstmgr_intersig_
mubi.1545157771
Directory /workspace/8.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/8.pwrmgr_smoke.4135376455
Short name T398
Test name
Test status
Simulation time 30431566 ps
CPU time 0.71 seconds
Started Aug 06 07:49:00 PM PDT 24
Finished Aug 06 07:49:01 PM PDT 24
Peak memory 199340 kb
Host smart-86f52eba-e8ae-4104-a0f6-8951b388b61b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135376455 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_smoke.4135376455
Directory /workspace/8.pwrmgr_smoke/latest

Test location /workspace/coverage/default/9.pwrmgr_aborted_low_power.1030523783
Short name T276
Test name
Test status
Simulation time 16467346 ps
CPU time 0.65 seconds
Started Aug 06 07:49:26 PM PDT 24
Finished Aug 06 07:49:26 PM PDT 24
Peak memory 199168 kb
Host smart-73847e39-10e1-4e25-b64b-97a417ee7fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030523783 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_aborted_low_power.1030523783
Directory /workspace/9.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/9.pwrmgr_disable_rom_integrity_check.4194993400
Short name T152
Test name
Test status
Simulation time 54566002 ps
CPU time 0.87 seconds
Started Aug 06 07:49:26 PM PDT 24
Finished Aug 06 07:49:27 PM PDT 24
Peak memory 199196 kb
Host smart-cdaa8217-9b67-4b13-8d82-3bac574597b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194993400 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_disa
ble_rom_integrity_check.4194993400
Directory /workspace/9.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/9.pwrmgr_esc_clk_rst_malfunc.1298584939
Short name T596
Test name
Test status
Simulation time 38312651 ps
CPU time 0.6 seconds
Started Aug 06 07:49:28 PM PDT 24
Finished Aug 06 07:49:28 PM PDT 24
Peak memory 197332 kb
Host smart-93d929ca-090f-4ce1-8fb7-e8b6d30ee85f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298584939 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_esc_clk_rst_
malfunc.1298584939
Directory /workspace/9.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/9.pwrmgr_escalation_timeout.3964290874
Short name T221
Test name
Test status
Simulation time 161680321 ps
CPU time 0.95 seconds
Started Aug 06 07:49:29 PM PDT 24
Finished Aug 06 07:49:30 PM PDT 24
Peak memory 198120 kb
Host smart-7e171a15-1466-40b5-969d-a3a78d69e742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964290874 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_escalation_timeout.3964290874
Directory /workspace/9.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/9.pwrmgr_glitch.250455773
Short name T342
Test name
Test status
Simulation time 38229870 ps
CPU time 0.65 seconds
Started Aug 06 07:49:29 PM PDT 24
Finished Aug 06 07:49:29 PM PDT 24
Peak memory 198024 kb
Host smart-46374ec0-9c95-4000-921d-6cfb9f277096
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250455773 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_glitch.250455773
Directory /workspace/9.pwrmgr_glitch/latest

Test location /workspace/coverage/default/9.pwrmgr_global_esc.2814483198
Short name T510
Test name
Test status
Simulation time 42633881 ps
CPU time 0.61 seconds
Started Aug 06 07:49:28 PM PDT 24
Finished Aug 06 07:49:29 PM PDT 24
Peak memory 198104 kb
Host smart-69431666-64ad-4a8b-9394-42614c7a56bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814483198 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_global_esc.2814483198
Directory /workspace/9.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/9.pwrmgr_lowpower_invalid.3197645843
Short name T192
Test name
Test status
Simulation time 151772460 ps
CPU time 0.67 seconds
Started Aug 06 07:49:28 PM PDT 24
Finished Aug 06 07:49:29 PM PDT 24
Peak memory 201376 kb
Host smart-5e79a967-24d7-45a7-be02-2551ef0708fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197645843 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_lowpower_invali
d.3197645843
Directory /workspace/9.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/9.pwrmgr_reset.2233003519
Short name T272
Test name
Test status
Simulation time 44523991 ps
CPU time 0.61 seconds
Started Aug 06 07:49:24 PM PDT 24
Finished Aug 06 07:49:25 PM PDT 24
Peak memory 198116 kb
Host smart-8de90686-0ec1-4ae1-9ec3-c24ca631cbfb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233003519 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset.2233003519
Directory /workspace/9.pwrmgr_reset/latest

Test location /workspace/coverage/default/9.pwrmgr_reset_invalid.444117319
Short name T407
Test name
Test status
Simulation time 183722872 ps
CPU time 0.83 seconds
Started Aug 06 07:49:26 PM PDT 24
Finished Aug 06 07:49:27 PM PDT 24
Peak memory 209548 kb
Host smart-9e7dbe07-48ce-443d-bbf5-a70dd8e6ea60
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444117319 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset_invalid.444117319
Directory /workspace/9.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/9.pwrmgr_sec_cm_rstmgr_intersig_mubi.2373536781
Short name T485
Test name
Test status
Simulation time 125525225 ps
CPU time 0.76 seconds
Started Aug 06 07:49:30 PM PDT 24
Finished Aug 06 07:49:31 PM PDT 24
Peak memory 198172 kb
Host smart-64d8f4d9-a245-4f3c-b882-7918d0129712
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373536781 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2373536781
Directory /workspace/9.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/9.pwrmgr_smoke.2585188463
Short name T603
Test name
Test status
Simulation time 118986179 ps
CPU time 0.62 seconds
Started Aug 06 07:49:28 PM PDT 24
Finished Aug 06 07:49:29 PM PDT 24
Peak memory 198516 kb
Host smart-7eb84637-98ba-4223-b187-576a293f8165
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585188463 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_smoke.2585188463
Directory /workspace/9.pwrmgr_smoke/latest
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