Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	41444	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

31800

1

T1

206

T2

19

T3

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	37749	1			T1	344		T2	21		T3	7
values[0x0]	17413	1			T1	66		T2	7		T3	11
values[0x1]	18082	1			T1	78		T2	9		T3	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	33057	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

40187

1

T1

256

T2

20

T3

10

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	427	1			T1	1		T6	2		T42	1
valid_sources[0x01]	276	1			T3	1		T74	2		T199	3
valid_sources[0x02]	234	1			T6	1		T199	3		T38	7
valid_sources[0x03]	192	1			T1	3		T45	1		T74	3
valid_sources[0x04]	229	1			T6	2		T74	2		T16	3
valid_sources[0x05]	330	1			T6	1		T74	1		T49	1
valid_sources[0x06]	316	1			T1	5		T13	2		T44	1
valid_sources[0x07]	259	1			T5	1		T13	2		T16	4
valid_sources[0x08]	232	1			T13	1		T75	2		T200	1
valid_sources[0x09]	191	1			T1	2		T2	1		T6	2
valid_sources[0x0a]	453	1			T1	4		T2	1		T6	1
valid_sources[0x0b]	299	1			T23	4		T13	2		T75	1
valid_sources[0x0c]	301	1			T6	1		T58	1		T74	2
valid_sources[0x0d]	302	1			T6	1		T39	1		T90	1
valid_sources[0x0e]	260	1			T13	1		T39	1		T80	1
valid_sources[0x0f]	199	1			T1	1		T2	1		T13	3
valid_sources[0x10]	242	1			T6	2		T14	1		T49	2
valid_sources[0x11]	172	1			T6	1		T13	2		T38	2
valid_sources[0x12]	247	1			T1	5		T2	1		T3	1
valid_sources[0x13]	278	1			T13	2		T74	1		T16	1
valid_sources[0x14]	217	1			T1	2		T45	1		T74	1
valid_sources[0x15]	373	1			T2	1		T6	1		T49	1
valid_sources[0x16]	267	1			T6	1		T199	2		T89	1
valid_sources[0x17]	321	1			T5	7		T6	4		T42	1
valid_sources[0x18]	236	1			T13	1		T80	1		T124	1
valid_sources[0x19]	547	1			T1	1		T18	1		T74	1
valid_sources[0x1a]	397	1			T1	1		T58	3		T14	1
valid_sources[0x1b]	237	1			T2	1		T6	1		T28	5
valid_sources[0x1c]	224	1			T6	1		T28	5		T58	1
valid_sources[0x1d]	237	1			T1	3		T13	2		T15	12
valid_sources[0x1e]	438	1			T30	5		T13	1		T74	1
valid_sources[0x1f]	210	1			T1	7		T13	2		T28	6
valid_sources[0x20]	216	1			T1	1		T58	1		T14	1
valid_sources[0x21]	186	1			T1	3		T6	2		T13	2
valid_sources[0x22]	236	1			T13	1		T59	1		T75	1
valid_sources[0x23]	274	1			T1	20		T6	2		T13	1
valid_sources[0x24]	219	1			T1	3		T13	1		T16	1
valid_sources[0x25]	196	1			T49	1		T90	3		T138	1
valid_sources[0x26]	202	1			T6	1		T13	5		T38	10
valid_sources[0x27]	201	1			T5	4		T13	1		T58	3
valid_sources[0x28]	309	1			T3	3		T13	1		T28	1
valid_sources[0x29]	195	1			T6	1		T7	2		T49	1
valid_sources[0x2a]	234	1			T6	6		T23	1		T13	2
valid_sources[0x2b]	471	1			T6	1		T13	1		T16	1
valid_sources[0x2c]	249	1			T1	7		T13	2		T49	1
valid_sources[0x2d]	227	1			T1	2		T6	1		T13	2
valid_sources[0x2e]	206	1			T75	1		T16	1		T199	1
valid_sources[0x2f]	214	1			T6	3		T13	1		T16	4
valid_sources[0x30]	236	1			T1	11		T6	2		T13	3
valid_sources[0x31]	327	1			T1	3		T6	3		T23	2
valid_sources[0x32]	193	1			T1	8		T13	1		T44	1
valid_sources[0x33]	287	1			T6	2		T29	34		T13	2
valid_sources[0x34]	264	1			T7	1		T44	1		T49	1
valid_sources[0x35]	220	1			T5	4		T6	1		T16	2
valid_sources[0x36]	473	1			T13	2		T75	1		T200	2
valid_sources[0x37]	313	1			T6	1		T42	1		T58	1
valid_sources[0x38]	479	1			T6	3		T9	1		T58	1
valid_sources[0x39]	290	1			T2	1		T5	3		T6	3
valid_sources[0x3a]	226	1			T74	1		T49	1		T16	2
valid_sources[0x3b]	526	1			T13	2		T75	1		T16	2
valid_sources[0x3c]	325	1			T6	2		T45	3		T16	3
valid_sources[0x3d]	305	1			T6	1		T42	2		T13	3
valid_sources[0x3e]	209	1			T1	1		T6	4		T74	2
valid_sources[0x3f]	145	1			T23	1		T74	2		T75	1
valid_sources[0x40]	244	1			T1	5		T6	1		T75	1
valid_sources[0x41]	278	1			T1	5		T6	2		T13	1
valid_sources[0x42]	297	1			T2	1		T6	1		T58	4
valid_sources[0x43]	271	1			T6	1		T42	1		T13	1
valid_sources[0x44]	296	1			T6	2		T28	9		T58	1
valid_sources[0x45]	300	1			T6	1		T13	1		T14	1
valid_sources[0x46]	174	1			T90	1		T91	1		T85	2
valid_sources[0x47]	282	1			T1	8		T16	2		T199	1
valid_sources[0x48]	219	1			T6	1		T14	1		T49	1
valid_sources[0x49]	260	1			T6	1		T42	3		T13	2
valid_sources[0x4a]	371	1			T13	2		T14	1		T44	1
valid_sources[0x4b]	284	1			T1	4		T6	1		T58	1
valid_sources[0x4c]	194	1			T6	3		T30	3		T13	2
valid_sources[0x4d]	191	1			T6	1		T13	4		T76	1
valid_sources[0x4e]	305	1			T1	1		T16	3		T39	1
valid_sources[0x4f]	173	1			T1	7		T2	1		T6	2
valid_sources[0x50]	247	1			T6	1		T13	2		T49	1
valid_sources[0x51]	279	1			T6	2		T16	3		T200	7
valid_sources[0x52]	293	1			T42	2		T13	1		T58	1
valid_sources[0x53]	262	1			T6	2		T13	1		T45	1
valid_sources[0x54]	237	1			T1	1		T13	6		T58	1
valid_sources[0x55]	251	1			T6	1		T38	1		T91	1
valid_sources[0x56]	359	1			T6	1		T13	3		T27	1
valid_sources[0x57]	241	1			T1	4		T6	1		T14	1
valid_sources[0x58]	246	1			T13	2		T58	1		T14	1
valid_sources[0x59]	233	1			T42	2		T13	3		T74	1
valid_sources[0x5a]	246	1			T6	1		T51	1		T16	2
valid_sources[0x5b]	560	1			T6	2		T13	3		T58	1
valid_sources[0x5c]	299	1			T6	1		T23	2		T13	2
valid_sources[0x5d]	322	1			T1	5		T3	2		T13	2
valid_sources[0x5e]	212	1			T1	4		T13	3		T74	1
valid_sources[0x5f]	255	1			T13	5		T51	5		T199	1
valid_sources[0x60]	324	1			T1	6		T6	1		T16	2
valid_sources[0x61]	217	1			T2	1		T30	3		T13	1
valid_sources[0x62]	276	1			T58	1		T16	2		T79	1
valid_sources[0x63]	258	1			T1	4		T2	1		T6	3
valid_sources[0x64]	256	1			T6	3		T13	3		T44	1
valid_sources[0x65]	268	1			T1	4		T13	1		T74	1
valid_sources[0x66]	563	1			T44	1		T49	1		T79	1
valid_sources[0x67]	287	1			T6	4		T14	1		T16	1
valid_sources[0x68]	286	1			T1	1		T13	1		T58	2
valid_sources[0x69]	314	1			T2	1		T6	1		T42	1
valid_sources[0x6a]	369	1			T6	1		T42	3		T16	1
valid_sources[0x6b]	301	1			T1	11		T6	2		T13	2
valid_sources[0x6c]	316	1			T7	8		T14	1		T74	1
valid_sources[0x6d]	210	1			T6	4		T13	1		T58	1
valid_sources[0x6e]	240	1			T1	23		T13	2		T14	3
valid_sources[0x6f]	647	1			T1	2		T13	4		T16	2
valid_sources[0x70]	455	1			T2	1		T58	1		T45	1
valid_sources[0x71]	693	1			T13	2		T58	1		T74	1
valid_sources[0x72]	296	1			T1	6		T13	1		T49	1
valid_sources[0x73]	301	1			T1	10		T6	1		T13	1
valid_sources[0x74]	493	1			T6	1		T15	2		T44	2
valid_sources[0x75]	299	1			T6	2		T13	5		T14	1
valid_sources[0x76]	299	1			T1	2		T3	1		T6	1
valid_sources[0x77]	205	1			T2	1		T44	1		T16	3
valid_sources[0x78]	255	1			T1	2		T13	1		T74	2
valid_sources[0x79]	606	1			T6	2		T13	6		T51	2
valid_sources[0x7a]	244	1			T7	2		T14	1		T16	4
valid_sources[0x7b]	234	1			T1	9		T6	1		T13	4
valid_sources[0x7c]	283	1			T6	1		T13	6		T58	1
valid_sources[0x7d]	286	1			T7	7		T30	3		T74	1
valid_sources[0x7e]	282	1			T14	1		T49	1		T80	1
valid_sources[0x7f]	189	1			T2	1		T13	2		T51	2
valid_sources[0x80]	229	1			T13	1		T58	1		T74	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

15890

1

T1

164

T2

14

T3

3

values[0x0]

all_enables

biggest_size

9029

1

T1

24

T2

3

T3

5

values[0x1]

all_enables

biggest_size

6881

1

T1

18

T2

2

T4

3