Unified Coverage Report :: Group :: dv_base_reg_pkg::dv_base_lockable_field_cov::regwen_val_when_new_value_written_cg

Group : dv_base_reg_pkg::dv_base_lockable_field_cov::regwen_val_when_new_value_written_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	75.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_dv_base_reg_0/dv_base_lockable_field_cov.sv

14 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
lockable_field_cov_of_pwrmgr_reg_block.control.low_power_hint	0.00	1	100	1	64	64
lockable_field_cov_of_pwrmgr_reg_block.control.core_clk_en	50.00	1	100	1	64	64
lockable_field_cov_of_pwrmgr_reg_block.control.io_clk_en	50.00	1	100	1	64	64
lockable_field_cov_of_pwrmgr_reg_block.control.main_pd_n	50.00	1	100	1	64	64
lockable_field_cov_of_pwrmgr_reg_block.control.usb_clk_en_active	50.00	1	100	1	64	64
lockable_field_cov_of_pwrmgr_reg_block.control.usb_clk_en_lp	50.00	1	100	1	64	64
lockable_field_cov_of_pwrmgr_reg_block.reset_en.en_0	100.00	1	100	1	64	64
lockable_field_cov_of_pwrmgr_reg_block.reset_en.en_1	100.00	1	100	1	64	64
lockable_field_cov_of_pwrmgr_reg_block.wakeup_en.en_0	100.00	1	100	1	64	64
lockable_field_cov_of_pwrmgr_reg_block.wakeup_en.en_1	100.00	1	100	1	64	64
lockable_field_cov_of_pwrmgr_reg_block.wakeup_en.en_2	100.00	1	100	1	64	64
lockable_field_cov_of_pwrmgr_reg_block.wakeup_en.en_3	100.00	1	100	1	64	64
lockable_field_cov_of_pwrmgr_reg_block.wakeup_en.en_4	100.00	1	100	1	64	64
lockable_field_cov_of_pwrmgr_reg_block.wakeup_en.en_5	100.00	1	100	1	64	64

---

Group Instance : lockable_field_cov_of_pwrmgr_reg_block.control.low_power_hint

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
0.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_pwrmgr_reg_block.control.low_power_hint

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	2	0	0.00

Variables for Group Instance lockable_field_cov_of_pwrmgr_reg_block.control.low_power_hint

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	2	0	0.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_pwrmgr_reg_block.control.core_clk_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
50.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_pwrmgr_reg_block.control.core_clk_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	1	1	50.00

Variables for Group Instance lockable_field_cov_of_pwrmgr_reg_block.control.core_clk_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	1	1	50.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_pwrmgr_reg_block.control.io_clk_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
50.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_pwrmgr_reg_block.control.io_clk_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	1	1	50.00

Variables for Group Instance lockable_field_cov_of_pwrmgr_reg_block.control.io_clk_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	1	1	50.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_pwrmgr_reg_block.control.main_pd_n

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
50.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_pwrmgr_reg_block.control.main_pd_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	1	1	50.00

Variables for Group Instance lockable_field_cov_of_pwrmgr_reg_block.control.main_pd_n

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	1	1	50.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_pwrmgr_reg_block.control.usb_clk_en_active

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
50.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_pwrmgr_reg_block.control.usb_clk_en_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	1	1	50.00

Variables for Group Instance lockable_field_cov_of_pwrmgr_reg_block.control.usb_clk_en_active

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	1	1	50.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_pwrmgr_reg_block.control.usb_clk_en_lp

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
50.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_pwrmgr_reg_block.control.usb_clk_en_lp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	1	1	50.00

Variables for Group Instance lockable_field_cov_of_pwrmgr_reg_block.control.usb_clk_en_lp

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	1	1	50.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_pwrmgr_reg_block.reset_en.en_0

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_pwrmgr_reg_block.reset_en.en_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_pwrmgr_reg_block.reset_en.en_0

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_pwrmgr_reg_block.reset_en.en_1

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_pwrmgr_reg_block.reset_en.en_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_pwrmgr_reg_block.reset_en.en_1

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_pwrmgr_reg_block.wakeup_en.en_0

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_pwrmgr_reg_block.wakeup_en.en_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_pwrmgr_reg_block.wakeup_en.en_0

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_pwrmgr_reg_block.wakeup_en.en_1

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_pwrmgr_reg_block.wakeup_en.en_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_pwrmgr_reg_block.wakeup_en.en_1

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_pwrmgr_reg_block.wakeup_en.en_2

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_pwrmgr_reg_block.wakeup_en.en_2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_pwrmgr_reg_block.wakeup_en.en_2

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_pwrmgr_reg_block.wakeup_en.en_3

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_pwrmgr_reg_block.wakeup_en.en_3

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_pwrmgr_reg_block.wakeup_en.en_3

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_pwrmgr_reg_block.wakeup_en.en_4

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_pwrmgr_reg_block.wakeup_en.en_4

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_pwrmgr_reg_block.wakeup_en.en_4

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_pwrmgr_reg_block.wakeup_en.en_5

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_pwrmgr_reg_block.wakeup_en.en_5

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_pwrmgr_reg_block.wakeup_en.en_5

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_regwen

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_regwen

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

562

1

T24

1

T26

11

T54

6

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_regwen

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

531

1

T24

1

T26

10

T54

12

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_regwen

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

541

1

T26

7

T54

9

T102

1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_regwen

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

542

1

T24

1

T26

11

T54

8

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_regwen

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

543

1

T26

10

T54

13

T53

1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

310

1

T26

3

T54

2

T102

1

auto[1]

297

1

T24

1

T26

5

T54

8

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

297

1

T26

1

T102

1

T55

2

auto[1]

288

1

T24

1

T26

8

T54

6

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

358

1

T26

4

T53

1

T55

1

auto[1]

263

1

T24

2

T26

8

T54

10

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

351

1

T26

3

T54

2

T53

1

auto[1]

248

1

T26

10

T54

10

T55

8

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

353

1

T26

2

T54

1

T53

1

auto[1]

236

1

T26

7

T54

6

T119

2

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

344

1

T26

3

T54

4

T53

2

auto[1]

215

1

T26

4

T54

10

T129

1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

338

1

T26

2

T54

2

T53

1

auto[1]

254

1

T24

1

T26

13

T54

9

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

334

1

T26

2

T54

2

T53

1

auto[1]

249

1

T26

8

T54

11

T102

1