SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 9 | 1 | T23 | 1 | T44 | 1 | T154 | 1 | ||||
others[1] | 9 | 1 | T7 | 1 | T139 | 1 | T150 | 1 | ||||
others[2] | 8 | 1 | T128 | 1 | T150 | 1 | T163 | 1 | ||||
others[3] | 21 | 1 | T23 | 1 | T36 | 2 | T139 | 2 | ||||
false | 120 | 1 | T7 | 2 | T23 | 3 | T28 | 5 | ||||
true | 2632 | 1 | T1 | 1 | T2 | 5 | T3 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 9 | 1 | T36 | 2 | T128 | 1 | T139 | 1 | ||||
others[1] | 18 | 1 | T23 | 1 | T36 | 1 | T138 | 1 | ||||
others[2] | 13 | 1 | T43 | 1 | T140 | 2 | T162 | 1 | ||||
others[3] | 15 | 1 | T28 | 1 | T44 | 1 | T164 | 3 | ||||
false | 136 | 1 | T7 | 4 | T23 | 3 | T28 | 3 | ||||
true | 2723 | 1 | T1 | 1 | T2 | 5 | T3 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 302 | 1 | T4 | 7 | T42 | 1 | T74 | 5 | ||||
others[1] | 350 | 1 | T4 | 7 | T42 | 1 | T74 | 8 | ||||
others[2] | 357 | 1 | T4 | 3 | T6 | 1 | T8 | 1 | ||||
others[3] | 545 | 1 | T4 | 9 | T6 | 1 | T7 | 2 | ||||
false | 3749 | 1 | T1 | 1 | T2 | 5 | T3 | 5 | ||||
true | 821 | 1 | T4 | 1 | T6 | 5 | T7 | 1 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |