Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	2204193	149	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	2204193	12959	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	2204193	150526	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	2204193	12959	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	2204193	149	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	2204193	12959	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	2204193	150526	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	2204193	12959	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2204193	149	0	0
T2	1409	1	0	0
T3	1512	1	0	0
T4	1856	0	0	0
T5	2532	2	0	0
T6	7003	0	0	0
T7	4485	0	0	0
T8	3356	0	0	0
T9	1026	0	0	0
T10	15067	0	0	0
T14	0	1	0	0
T29	1258	0	0	0
T49	0	1	0	0
T51	0	1	0	0
T58	0	1	0	0
T61	0	1	0	0
T77	0	2	0	0
T78	0	1	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2204193	12959	0	0
T2	1409	85	0	0
T3	1512	96	0	0
T4	1856	0	0	0
T5	2532	318	0	0
T6	7003	0	0	0
T7	4485	0	0	0
T8	3356	0	0	0
T9	1026	0	0	0
T10	15067	0	0	0
T14	0	12	0	0
T29	1258	0	0	0
T49	0	12	0	0
T51	0	10	0	0
T58	0	84	0	0
T61	0	187	0	0
T77	0	163	0	0
T78	0	15	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2204193	150526	0	0
T1	3080	865	0	0
T2	1409	626	0	0
T3	1512	563	0	0
T4	1856	0	0	0
T5	2532	186	0	0
T6	7003	0	0	0
T7	4485	0	0	0
T8	3356	0	0	0
T9	1026	0	0	0
T10	15067	0	0	0
T13	0	1154	0	0
T14	0	1067	0	0
T15	0	2528	0	0
T49	0	1509	0	0
T58	0	96	0	0
T61	0	99	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2204193	12959	0	0
T2	1409	85	0	0
T3	1512	96	0	0
T4	1856	0	0	0
T5	2532	318	0	0
T6	7003	0	0	0
T7	4485	0	0	0
T8	3356	0	0	0
T9	1026	0	0	0
T10	15067	0	0	0
T14	0	12	0	0
T29	1258	0	0	0
T49	0	12	0	0
T51	0	10	0	0
T58	0	84	0	0
T61	0	187	0	0
T77	0	163	0	0
T78	0	15	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2204193	149	0	0
T2	1409	1	0	0
T3	1512	1	0	0
T4	1856	0	0	0
T5	2532	2	0	0
T6	7003	0	0	0
T7	4485	0	0	0
T8	3356	0	0	0
T9	1026	0	0	0
T10	15067	0	0	0
T14	0	1	0	0
T29	1258	0	0	0
T49	0	1	0	0
T51	0	1	0	0
T58	0	1	0	0
T61	0	1	0	0
T77	0	2	0	0
T78	0	1	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2204193	12959	0	0
T2	1409	85	0	0
T3	1512	96	0	0
T4	1856	0	0	0
T5	2532	318	0	0
T6	7003	0	0	0
T7	4485	0	0	0
T8	3356	0	0	0
T9	1026	0	0	0
T10	15067	0	0	0
T14	0	12	0	0
T29	1258	0	0	0
T49	0	12	0	0
T51	0	10	0	0
T58	0	84	0	0
T61	0	187	0	0
T77	0	163	0	0
T78	0	15	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2204193	150526	0	0
T1	3080	865	0	0
T2	1409	626	0	0
T3	1512	563	0	0
T4	1856	0	0	0
T5	2532	186	0	0
T6	7003	0	0	0
T7	4485	0	0	0
T8	3356	0	0	0
T9	1026	0	0	0
T10	15067	0	0	0
T13	0	1154	0	0
T14	0	1067	0	0
T15	0	2528	0	0
T49	0	1509	0	0
T58	0	96	0	0
T61	0	99	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2204193	12959	0	0
T2	1409	85	0	0
T3	1512	96	0	0
T4	1856	0	0	0
T5	2532	318	0	0
T6	7003	0	0	0
T7	4485	0	0	0
T8	3356	0	0	0
T9	1026	0	0	0
T10	15067	0	0	0
T14	0	12	0	0
T29	1258	0	0	0
T49	0	12	0	0
T51	0	10	0	0
T58	0	84	0	0
T61	0	187	0	0
T77	0	163	0	0
T78	0	15	0	0