Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2761781	15744	0	0
intr_enable_rd_A	2761781	2488	0	0
reset_en_rd_A	2761781	977	0	0
reset_en_regwen_rd_A	2761781	1085	0	0
wake_info_capture_dis_rd_A	2761781	961	0	0
wakeup_en_rd_A	2761781	1629	0	0
wakeup_en_regwen_rd_A	2761781	953	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2761781	15744	0	0
T24	2366	54	0	0
T25	10753	764	0	0
T26	7059	11	0	0
T53	1828	220	0	0
T54	13340	11	0	0
T55	8006	5	0	0
T56	3133	715	0	0
T62	2147	348	0	0
T63	3519	794	0	0
T64	2073	79	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2761781	2488	0	0
T41	4802	8	0	0
T80	1406	0	0	0
T81	0	3	0	0
T82	0	4	0	0
T84	2841	0	0	0
T86	0	91	0	0
T87	1179	0	0	0
T88	2915	0	0	0
T89	2623	0	0	0
T90	3244	0	0	0
T91	1945	0	0	0
T92	1595	0	0	0
T95	0	22	0	0
T96	0	51	0	0
T97	0	30	0	0
T125	0	27	0	0
T126	0	71	0	0
T127	0	2	0	0
T128	1876	0	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2761781	977	0	0
T24	2366	5	0	0
T25	10753	31	0	0
T70	10083	8	0	0
T71	8884	51	0	0
T103	1425	7	0	0
T115	2780	16	0	0
T117	2446	23	0	0
T129	1698	9	0	0
T130	2468	9	0	0
T131	11723	13	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2761781	1085	0	0
T24	2366	11	0	0
T25	10753	10	0	0
T70	10083	15	0	0
T71	8884	45	0	0
T103	1425	14	0	0
T115	2780	29	0	0
T117	2446	37	0	0
T129	1698	2	0	0
T130	2468	18	0	0
T131	11723	10	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2761781	961	0	0
T24	2366	14	0	0
T25	10753	10	0	0
T70	10083	12	0	0
T71	8884	34	0	0
T103	1425	5	0	0
T115	2780	8	0	0
T129	1698	3	0	0
T130	2468	18	0	0
T131	11723	7	0	0
T132	3095	16	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2761781	1629	0	0
T24	2366	10	0	0
T25	10753	19	0	0
T70	10083	32	0	0
T71	8884	154	0	0
T103	1425	20	0	0
T115	2780	31	0	0
T117	2446	10	0	0
T129	1698	2	0	0
T130	2468	9	0	0
T131	11723	18	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2761781	953	0	0
T24	2366	5	0	0
T25	10753	12	0	0
T70	10083	35	0	0
T71	8884	56	0	0
T103	1425	8	0	0
T115	2780	3	0	0
T117	2446	10	0	0
T129	1698	3	0	0
T130	2468	5	0	0
T131	11723	18	0	0