Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	6612579	9492	0	0
StatusRise_A	6612579	12863	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6612579	9492	0	0
T1	9240	46	0	0
T2	4227	12	0	0
T3	4536	12	0	0
T4	5568	3	0	0
T5	7596	12	0	0
T6	21009	54	0	0
T7	13455	21	0	0
T8	10068	21	0	0
T9	3078	0	0	0
T10	45201	3	0	0
T29	0	12	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6612579	12863	0	0
T1	9240	48	0	0
T2	4227	15	0	0
T3	4536	15	0	0
T4	5568	6	0	0
T5	7596	15	0	0
T6	21009	60	0	0
T7	13455	24	0	0
T8	10068	27	0	0
T9	3078	12	0	0
T10	45201	6	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	2204193	3215	0	0
StatusRise_A	2204193	4349	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2204193	3215	0	0
T1	3080	18	0	0
T2	1409	4	0	0
T3	1512	4	0	0
T4	1856	1	0	0
T5	2532	4	0	0
T6	7003	18	0	0
T7	4485	7	0	0
T8	3356	7	0	0
T9	1026	0	0	0
T10	15067	1	0	0
T29	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2204193	4349	0	0
T1	3080	19	0	0
T2	1409	5	0	0
T3	1512	5	0	0
T4	1856	2	0	0
T5	2532	5	0	0
T6	7003	20	0	0
T7	4485	8	0	0
T8	3356	9	0	0
T9	1026	4	0	0
T10	15067	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	2204193	3215	0	0
StatusRise_A	2204193	4349	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2204193	3215	0	0
T1	3080	18	0	0
T2	1409	4	0	0
T3	1512	4	0	0
T4	1856	1	0	0
T5	2532	4	0	0
T6	7003	18	0	0
T7	4485	7	0	0
T8	3356	7	0	0
T9	1026	0	0	0
T10	15067	1	0	0
T29	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2204193	4349	0	0
T1	3080	19	0	0
T2	1409	5	0	0
T3	1512	5	0	0
T4	1856	2	0	0
T5	2532	5	0	0
T6	7003	20	0	0
T7	4485	8	0	0
T8	3356	9	0	0
T9	1026	4	0	0
T10	15067	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	2204193	3062	0	0
StatusRise_A	2204193	4165	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2204193	3062	0	0
T1	3080	10	0	0
T2	1409	4	0	0
T3	1512	4	0	0
T4	1856	1	0	0
T5	2532	4	0	0
T6	7003	18	0	0
T7	4485	7	0	0
T8	3356	7	0	0
T9	1026	0	0	0
T10	15067	1	0	0
T29	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2204193	4165	0	0
T1	3080	10	0	0
T2	1409	5	0	0
T3	1512	5	0	0
T4	1856	2	0	0
T5	2532	5	0	0
T6	7003	20	0	0
T7	4485	8	0	0
T8	3356	9	0	0
T9	1026	4	0	0
T10	15067	2	0	0