Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	2204565	5884	0	0
EscTimeoutStoppedByClReset_A	2204193	71024	0	0
EscTimeoutTriggersReset_A	306740	301	0	0
RomAllowActiveState_A	2204193	3982	0	0
RomAllowCheckGoodState_A	2204193	4038	0	0
RomBlockActiveState_A	2204193	30051	0	0
RomBlockCheckGoodState_A	2204193	20422	0	0
RomIntgChkDisFalse_A	2204193	2018653	0	0
RomIntgChkDisTrue_A	2204193	35900	0	0
RstreqChkEsctimeout_A	2204193	1012	0	0
RstreqChkFsmterm_A	2204193	100	0	0
RstreqChkGlbesc_A	2204193	1012	0	0
RstreqChkMainpd_A	2204193	51153	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2204565	5884	0	0
T10	15068	8	0	0
T11	0	20	0	0
T12	0	10	0	0
T13	2583	0	0	0
T14	1509	0	0	0
T23	5301	0	0	0
T28	5667	0	0	0
T29	1258	0	0	0
T30	1342	0	0	0
T42	3796	0	0	0
T43	4749	0	0	0
T58	2668	0	0	0
T87	0	16	0	0
T93	0	121	0	0
T94	0	146	0	0
T133	0	116	0	0
T134	0	96	0	0
T135	0	12	0	0
T136	0	231	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2204193	71024	0	0
T1	3080	30	0	0
T2	1409	73	0	0
T3	1512	54	0	0
T4	1856	9	0	0
T5	2532	61	0	0
T6	7003	457	0	0
T7	4485	241	0	0
T8	3356	377	0	0
T9	1026	1	0	0
T10	15067	23	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306740	301	0	0
T10	3176	3	0	0
T11	0	2	0	0
T12	0	6	0	0
T13	204	0	0	0
T14	260	0	0	0
T23	384	0	0	0
T28	429	0	0	0
T29	1055	0	0	0
T30	943	0	0	0
T42	286	0	0	0
T43	359	0	0	0
T58	278	0	0	0
T87	0	4	0	0
T93	0	3	0	0
T133	0	2	0	0
T134	0	2	0	0
T135	0	4	0	0
T136	0	3	0	0
T137	0	8	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2204193	3982	0	0
T1	3080	19	0	0
T2	1409	5	0	0
T3	1512	5	0	0
T4	1856	2	0	0
T5	2532	5	0	0
T6	7003	13	0	0
T7	4485	8	0	0
T8	3356	9	0	0
T9	1026	4	0	0
T10	15067	2	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2204193	4038	0	0
T1	3080	19	0	0
T2	1409	5	0	0
T3	1512	5	0	0
T4	1856	2	0	0
T5	2532	5	0	0
T6	7003	14	0	0
T7	4485	8	0	0
T8	3356	9	0	0
T9	1026	4	0	0
T10	15067	2	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2204193	30051	0	0
T7	4485	600	0	0
T8	3356	0	0	0
T9	1026	0	0	0
T10	15067	0	0	0
T13	2583	0	0	0
T23	5300	1468	0	0
T28	5666	1142	0	0
T29	1258	0	0	0
T30	1342	0	0	0
T36	0	381	0	0
T42	3795	0	0	0
T43	0	903	0	0
T44	0	1119	0	0
T45	0	1057	0	0
T128	0	241	0	0
T138	0	590	0	0
T139	0	43	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2204193	20422	0	0
T7	4485	858	0	0
T8	3356	0	0	0
T9	1026	0	0	0
T10	15067	0	0	0
T13	2583	0	0	0
T23	5300	879	0	0
T28	5666	865	0	0
T29	1258	0	0	0
T30	1342	0	0	0
T36	0	348	0	0
T42	3795	0	0	0
T43	0	868	0	0
T44	0	890	0	0
T45	0	667	0	0
T128	0	68	0	0
T138	0	836	0	0
T140	0	369	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2204193	2018653	0	0
T1	3080	3027	0	0
T2	1409	1041	0	0
T3	1512	1111	0	0
T4	1856	1770	0	0
T5	2532	2097	0	0
T6	7003	6035	0	0
T7	4485	2433	0	0
T8	3356	3232	0	0
T9	1026	722	0	0
T10	15067	14992	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2204193	35900	0	0
T7	4485	1994	0	0
T8	3356	0	0	0
T9	1026	0	0	0
T10	15067	0	0	0
T13	2583	0	0	0
T23	5300	1713	0	0
T28	5666	2097	0	0
T29	1258	0	0	0
T30	1342	0	0	0
T42	3795	0	0	0
T43	0	1435	0	0
T44	0	316	0	0
T45	0	1954	0	0
T128	0	85	0	0
T138	0	1974	0	0
T139	0	566	0	0
T140	0	385	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2204193	1012	0	0
T6	7003	4	0	0
T7	4485	2	0	0
T8	3356	2	0	0
T9	1026	0	0	0
T10	15067	1	0	0
T11	0	1	0	0
T13	2583	0	0	0
T23	5300	2	0	0
T28	0	4	0	0
T29	1258	0	0	0
T30	1342	0	0	0
T42	3795	5	0	0
T43	0	2	0	0
T44	0	3	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2204193	100	0	0
T20	22971	20	0	0
T21	0	20	0	0
T22	0	20	0	0
T31	0	20	0	0
T32	0	20	0	0
T33	2238	0	0	0
T34	3068	0	0	0
T35	2865	0	0	0
T36	2679	0	0	0
T37	1087	0	0	0
T38	2472	0	0	0
T39	2560	0	0	0
T40	1436	0	0	0
T41	4802	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2204193	1012	0	0
T6	7003	4	0	0
T7	4485	2	0	0
T8	3356	2	0	0
T9	1026	0	0	0
T10	15067	1	0	0
T11	0	1	0	0
T13	2583	0	0	0
T23	5300	2	0	0
T28	0	4	0	0
T29	1258	0	0	0
T30	1342	0	0	0
T42	3795	5	0	0
T43	0	2	0	0
T44	0	3	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2204193	51153	0	0
T6	7003	165	0	0
T7	4485	631	0	0
T8	3356	386	0	0
T9	1026	10	0	0
T10	15067	0	0	0
T13	2583	0	0	0
T17	0	25	0	0
T23	5300	1285	0	0
T27	0	6	0	0
T28	0	1343	0	0
T29	1258	0	0	0
T30	1342	0	0	0
T42	3795	328	0	0
T43	0	1247	0	0