Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	532186	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

200423

1

T1

3704

T2

41

T3

19

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	378947	1			T1	7331		T2	69		T3	57
values[0x0]	176604	1			T1	2029		T2	33		T3	16
values[0x1]	177058	1			T1	2098		T2	42		T3	13

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	421785	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

310824

1

T1

5365

T2

67

T3

31

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2172	1			T1	5		T2	1		T4	1
valid_sources[0x01]	3136	1			T2	1		T6	28		T7	8
valid_sources[0x02]	2091	1			T6	39		T8	3		T20	2
valid_sources[0x03]	5261	1			T6	51		T7	3		T9	1
valid_sources[0x04]	12333	1			T6	31		T74	1		T20	7
valid_sources[0x05]	3194	1			T2	1		T6	26		T74	1
valid_sources[0x06]	2883	1			T2	1		T6	49		T20	8
valid_sources[0x07]	2095	1			T2	1		T6	46		T7	1
valid_sources[0x08]	2141	1			T2	3		T6	48		T7	8
valid_sources[0x09]	2335	1			T6	40		T7	6		T9	1
valid_sources[0x0a]	4098	1			T6	50		T74	1		T20	1
valid_sources[0x0b]	2395	1			T6	48		T7	3		T8	4
valid_sources[0x0c]	2527	1			T2	1		T6	53		T7	5
valid_sources[0x0d]	2536	1			T6	32		T7	1		T74	1
valid_sources[0x0e]	2242	1			T6	40		T13	36		T33	5
valid_sources[0x0f]	3095	1			T6	40		T7	3		T20	2
valid_sources[0x10]	3063	1			T1	7		T6	42		T74	5
valid_sources[0x11]	3112	1			T6	45		T7	7		T8	14
valid_sources[0x12]	7097	1			T6	48		T7	18		T74	1
valid_sources[0x13]	2597	1			T4	1		T6	52		T8	5
valid_sources[0x14]	2105	1			T1	5		T6	40		T7	12
valid_sources[0x15]	2527	1			T6	40		T74	1		T20	1
valid_sources[0x16]	2240	1			T1	5		T6	65		T7	7
valid_sources[0x17]	2550	1			T1	5		T6	49		T7	5
valid_sources[0x18]	4928	1			T6	42		T9	1		T74	1
valid_sources[0x19]	2389	1			T6	34		T7	1		T20	1
valid_sources[0x1a]	2297	1			T1	3		T6	35		T7	3
valid_sources[0x1b]	2360	1			T6	54		T20	4		T13	30
valid_sources[0x1c]	2467	1			T6	49		T7	6		T20	2
valid_sources[0x1d]	2423	1			T6	31		T7	3		T8	7
valid_sources[0x1e]	3163	1			T6	47		T7	6		T8	3
valid_sources[0x1f]	2196	1			T2	1		T6	37		T7	3
valid_sources[0x20]	4148	1			T1	5		T2	1		T6	35
valid_sources[0x21]	2329	1			T1	5		T6	60		T8	4
valid_sources[0x22]	2305	1			T2	1		T6	36		T7	1
valid_sources[0x23]	2854	1			T1	5		T6	36		T7	10
valid_sources[0x24]	2405	1			T6	33		T7	13		T8	1
valid_sources[0x25]	2161	1			T1	5		T2	1		T6	36
valid_sources[0x26]	5808	1			T1	2370		T6	31		T7	4
valid_sources[0x27]	2363	1			T6	61		T7	9		T20	4
valid_sources[0x28]	2197	1			T6	46		T7	5		T74	1
valid_sources[0x29]	2125	1			T6	48		T7	4		T8	9
valid_sources[0x2a]	2944	1			T6	40		T7	1		T9	2
valid_sources[0x2b]	2235	1			T5	85		T6	48		T7	8
valid_sources[0x2c]	2263	1			T6	39		T7	7		T13	36
valid_sources[0x2d]	3614	1			T1	5		T6	42		T7	8
valid_sources[0x2e]	3461	1			T4	1		T6	28		T7	6
valid_sources[0x2f]	2383	1			T1	10		T6	33		T7	2
valid_sources[0x30]	5816	1			T1	5		T6	45		T74	1
valid_sources[0x31]	2138	1			T1	5		T2	1		T6	44
valid_sources[0x32]	2126	1			T6	50		T74	3		T20	1
valid_sources[0x33]	3233	1			T6	54		T74	1		T20	1
valid_sources[0x34]	2597	1			T1	5		T6	36		T7	14
valid_sources[0x35]	3584	1			T2	1		T6	45		T7	1
valid_sources[0x36]	1923	1			T2	1		T6	45		T7	10
valid_sources[0x37]	2207	1			T4	1		T6	44		T9	1
valid_sources[0x38]	4242	1			T1	10		T6	57		T74	1
valid_sources[0x39]	2725	1			T1	5		T2	2		T6	44
valid_sources[0x3a]	4091	1			T6	37		T8	1		T74	1
valid_sources[0x3b]	2279	1			T2	4		T6	23		T8	14
valid_sources[0x3c]	2161	1			T2	1		T6	36		T7	2
valid_sources[0x3d]	3469	1			T6	34		T7	2		T74	1
valid_sources[0x3e]	2643	1			T6	54		T7	1		T74	2
valid_sources[0x3f]	2730	1			T1	5		T6	51		T8	1
valid_sources[0x40]	3401	1			T6	49		T7	27		T13	60
valid_sources[0x41]	2315	1			T2	1		T6	42		T7	3
valid_sources[0x42]	2978	1			T2	1		T6	41		T74	1
valid_sources[0x43]	2353	1			T6	36		T7	6		T9	1
valid_sources[0x44]	3196	1			T6	38		T7	1		T20	6
valid_sources[0x45]	2477	1			T2	1		T6	40		T7	14
valid_sources[0x46]	2196	1			T1	10		T2	1		T6	46
valid_sources[0x47]	3334	1			T6	49		T7	3		T74	1
valid_sources[0x48]	2321	1			T1	5		T2	1		T6	42
valid_sources[0x49]	2240	1			T1	5		T6	48		T74	1
valid_sources[0x4a]	3952	1			T6	47		T74	2		T20	6
valid_sources[0x4b]	3463	1			T1	5		T2	4		T4	1
valid_sources[0x4c]	2210	1			T6	39		T7	6		T8	1
valid_sources[0x4d]	2628	1			T1	5		T4	1		T6	38
valid_sources[0x4e]	3239	1			T1	5		T2	2		T4	1
valid_sources[0x4f]	2396	1			T4	1		T6	59		T7	11
valid_sources[0x50]	2290	1			T1	5		T4	1		T6	42
valid_sources[0x51]	2725	1			T1	5		T6	44		T7	9
valid_sources[0x52]	2349	1			T6	40		T13	36		T34	1
valid_sources[0x53]	2259	1			T1	5		T4	1		T6	42
valid_sources[0x54]	2391	1			T6	42		T7	1		T9	1
valid_sources[0x55]	2194	1			T6	42		T7	10		T8	1
valid_sources[0x56]	3545	1			T2	1		T6	42		T9	1
valid_sources[0x57]	2724	1			T2	2		T6	41		T7	21
valid_sources[0x58]	3610	1			T1	5		T6	41		T7	5
valid_sources[0x59]	3117	1			T1	19		T6	43		T20	6
valid_sources[0x5a]	4080	1			T1	10		T6	35		T7	1
valid_sources[0x5b]	3151	1			T2	3		T6	27		T8	3
valid_sources[0x5c]	8248	1			T1	5057		T2	1		T6	41
valid_sources[0x5d]	2131	1			T6	40		T7	10		T74	1
valid_sources[0x5e]	2401	1			T6	43		T7	2		T9	1
valid_sources[0x5f]	3619	1			T1	5		T2	1		T6	42
valid_sources[0x60]	2803	1			T1	15		T6	47		T8	1
valid_sources[0x61]	2361	1			T1	10		T2	2		T6	39
valid_sources[0x62]	2992	1			T2	1		T6	40		T7	3
valid_sources[0x63]	2961	1			T6	52		T74	4		T20	2
valid_sources[0x64]	3148	1			T2	2		T6	49		T7	1
valid_sources[0x65]	3967	1			T4	1		T6	42		T74	3
valid_sources[0x66]	4182	1			T1	5		T6	32		T8	8
valid_sources[0x67]	3219	1			T2	1		T6	57		T7	3
valid_sources[0x68]	2227	1			T2	2		T6	49		T74	2
valid_sources[0x69]	3645	1			T6	46		T7	6		T8	4
valid_sources[0x6a]	3034	1			T6	41		T7	12		T74	1
valid_sources[0x6b]	3020	1			T1	25		T6	46		T7	3
valid_sources[0x6c]	2352	1			T6	43		T7	7		T74	2
valid_sources[0x6d]	2717	1			T1	5		T6	27		T7	1
valid_sources[0x6e]	2400	1			T6	41		T7	7		T9	1
valid_sources[0x6f]	2025	1			T1	10		T6	51		T8	2
valid_sources[0x70]	2171	1			T6	49		T8	4		T9	1
valid_sources[0x71]	2388	1			T2	1		T6	35		T7	6
valid_sources[0x72]	2365	1			T6	47		T7	4		T20	1
valid_sources[0x73]	2294	1			T1	5		T6	36		T9	1
valid_sources[0x74]	2173	1			T1	6		T6	49		T7	3
valid_sources[0x75]	2408	1			T6	30		T74	5		T20	6
valid_sources[0x76]	2273	1			T2	1		T6	42		T7	4
valid_sources[0x77]	2131	1			T2	1		T6	43		T8	7
valid_sources[0x78]	2216	1			T1	10		T6	41		T7	3
valid_sources[0x79]	2717	1			T6	44		T7	5		T8	7
valid_sources[0x7a]	2907	1			T2	1		T6	36		T13	34
valid_sources[0x7b]	2207	1			T6	41		T7	12		T8	2
valid_sources[0x7c]	3297	1			T1	21		T6	34		T74	1
valid_sources[0x7d]	3589	1			T4	2		T6	60		T7	1
valid_sources[0x7e]	3341	1			T6	54		T7	11		T20	2
valid_sources[0x7f]	3612	1			T2	1		T6	39		T13	42
valid_sources[0x80]	2510	1			T1	5		T6	43		T9	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

99358

1

T1

2527

T2

18

T3

14

values[0x0]

all_enables

biggest_size

65649

1

T1

764

T2

15

T3

4

values[0x1]

all_enables

biggest_size

35416

1

T1

413

T2

8

T3

1