SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35188 | 1 | T7 | 427 | T20 | 275 | T34 | 374 | ||||
others[1] | 34975 | 1 | T5 | 1 | T7 | 371 | T20 | 313 | ||||
others[2] | 34918 | 1 | T5 | 1 | T7 | 390 | T20 | 304 | ||||
others[3] | 58414 | 1 | T7 | 680 | T20 | 524 | T34 | 693 | ||||
false | 20019 | 1 | T1 | 174 | T3 | 6 | T5 | 1 | ||||
true | 30279 | 1 | T1 | 252 | T2 | 1 | T3 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35145 | 1 | T5 | 1 | T7 | 403 | T20 | 294 | ||||
others[1] | 34852 | 1 | T5 | 1 | T7 | 410 | T20 | 313 | ||||
others[2] | 35012 | 1 | T7 | 381 | T20 | 320 | T34 | 404 | ||||
others[3] | 58435 | 1 | T5 | 1 | T7 | 677 | T20 | 463 | ||||
false | 12624 | 1 | T1 | 87 | T3 | 3 | T5 | 2 | ||||
true | 22939 | 1 | T1 | 165 | T2 | 1 | T3 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 702 | 1 | T1 | 5 | T6 | 12 | T13 | 9 | ||||
others[1] | 680 | 1 | T1 | 13 | T6 | 6 | T13 | 9 | ||||
others[2] | 738 | 1 | T1 | 8 | T6 | 5 | T13 | 7 | ||||
others[3] | 1167 | 1 | T1 | 16 | T5 | 1 | T6 | 7 | ||||
false | 14211 | 1 | T1 | 207 | T2 | 1 | T3 | 2 | ||||
true | 4242 | 1 | T1 | 88 | T5 | 2 | T6 | 74 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |