Unified Coverage Report :: Module :: pwrmgr_clock_enables_sva_if

Module : pwrmgr_clock_enables_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_clock_enables_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_clock_enables_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_clock_enables_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_clock_enables_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	30	1	1	100.00
ALWAYS	37	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_clock_enables_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_clock_enables_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
30	1	1
37	1	1

---

Cond Coverage for Module : pwrmgr_clock_enables_sva_if

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       30
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T6

 LINE       37
 EXPRESSION (fast_state == FastPwrStateActive)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_clock_enables_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CoreClkPwrDown_A	5756549	14388	0	0
CoreClkPwrUp_A	5756549	189893	0	0
IoClkPwrDown_A	5756549	14388	0	0
IoClkPwrUp_A	5756549	189893	0	0
UsbClkActive_A	5756549	3943	0	0
UsbClkPwrDown_A	5756549	14388	0	0
UsbClkPwrUp_A	5756549	189893	0	0

CoreClkPwrDown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5756549	14388	0	0
T1	42977	168	0	0
T2	1043	5	0	0
T3	544	1	0	0
T4	328	1	0	0
T5	420	0	0	0
T6	103442	239	0	0
T7	9475	27	0	0
T8	1585	9	0	0
T9	726	2	0	0
T10	232	0	0	0
T20	0	23	0	0
T74	0	8	0	0

CoreClkPwrUp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5756549	189893	0	0
T1	42977	1344	0	0
T2	1043	43	0	0
T3	544	17	0	0
T4	328	13	0	0
T5	420	0	0	0
T6	103442	3425	0	0
T7	9475	372	0	0
T8	1585	75	0	0
T9	726	17	0	0
T10	232	0	0	0
T20	0	287	0	0
T74	0	58	0	0

IoClkPwrDown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5756549	14388	0	0
T1	42977	168	0	0
T2	1043	5	0	0
T3	544	1	0	0
T4	328	1	0	0
T5	420	0	0	0
T6	103442	239	0	0
T7	9475	27	0	0
T8	1585	9	0	0
T9	726	2	0	0
T10	232	0	0	0
T20	0	23	0	0
T74	0	8	0	0

IoClkPwrUp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5756549	189893	0	0
T1	42977	1344	0	0
T2	1043	43	0	0
T3	544	17	0	0
T4	328	13	0	0
T5	420	0	0	0
T6	103442	3425	0	0
T7	9475	372	0	0
T8	1585	75	0	0
T9	726	17	0	0
T10	232	0	0	0
T20	0	287	0	0
T74	0	58	0	0

UsbClkActive_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5756549	3943	0	0
T1	42977	58	0	0
T2	1043	0	0	0
T3	544	0	0	0
T4	328	0	0	0
T5	420	0	0	0
T6	103442	79	0	0
T7	9475	0	0	0
T8	1585	0	0	0
T9	726	2	0	0
T10	232	0	0	0
T13	0	42	0	0
T33	0	6	0	0
T36	0	25	0	0
T38	0	41	0	0
T55	0	1	0	0
T75	0	5	0	0
T76	0	4	0	0

UsbClkPwrDown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5756549	14388	0	0
T1	42977	168	0	0
T2	1043	5	0	0
T3	544	1	0	0
T4	328	1	0	0
T5	420	0	0	0
T6	103442	239	0	0
T7	9475	27	0	0
T8	1585	9	0	0
T9	726	2	0	0
T10	232	0	0	0
T20	0	23	0	0
T74	0	8	0	0

UsbClkPwrUp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5756549	189893	0	0
T1	42977	1344	0	0
T2	1043	43	0	0
T3	544	17	0	0
T4	328	13	0	0
T5	420	0	0	0
T6	103442	3425	0	0
T7	9475	372	0	0
T8	1585	75	0	0
T9	726	17	0	0
T10	232	0	0	0
T20	0	287	0	0
T74	0	58	0	0