Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	25349625	15719	0	0
intr_enable_rd_A	25349625	39475	0	0
reset_en_rd_A	25349625	1045	0	0
reset_en_regwen_rd_A	25349625	966	0	0
wake_info_capture_dis_rd_A	25349625	827	0	0
wakeup_en_rd_A	25349625	1597	0	0
wakeup_en_regwen_rd_A	25349625	849	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25349625	15719	0	0
T1	415449	100	0	0
T2	9690	0	0	0
T3	4797	0	0	0
T4	1134	0	0	0
T5	5585	0	0	0
T6	281355	8	0	0
T7	25326	0	0	0
T8	12125	0	0	0
T9	3612	0	0	0
T10	15271	0	0	0
T13	0	2	0	0
T27	0	24	0	0
T31	0	21	0	0
T36	0	29	0	0
T38	0	26	0	0
T39	0	2	0	0
T78	0	18	0	0
T131	0	5	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25349625	39475	0	0
T7	25326	175	0	0
T8	12125	0	0	0
T9	3612	0	0	0
T10	15271	0	0	0
T11	655	0	0	0
T13	213567	0	0	0
T20	21044	0	0	0
T27	0	1214	0	0
T30	0	9	0	0
T33	153498	0	0	0
T34	22149	0	0	0
T74	14982	0	0	0
T76	0	68	0	0
T77	0	170	0	0
T127	0	18	0	0
T132	0	35	0	0
T133	0	161	0	0
T134	0	3	0	0
T135	0	8	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25349625	1045	0	0
T44	2870	0	0	0
T81	0	12	0	0
T90	0	8	0	0
T136	237324	2	0	0
T137	0	5	0	0
T138	0	5	0	0
T139	0	4	0	0
T140	0	12	0	0
T141	0	4	0	0
T142	0	9	0	0
T143	0	8	0	0
T144	2252	0	0	0
T145	4722	0	0	0
T146	8780	0	0	0
T147	3968	0	0	0
T148	54462	0	0	0
T149	3019	0	0	0
T150	3582	0	0	0
T151	3125	0	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25349625	966	0	0
T18	9180	0	0	0
T27	320993	5	0	0
T28	3747	0	0	0
T29	18571	0	0	0
T30	1234	0	0	0
T31	278381	0	0	0
T32	4458	0	0	0
T81	0	9	0	0
T82	0	1	0	0
T90	0	2	0	0
T96	1349	0	0	0
T136	0	4	0	0
T137	0	2	0	0
T139	0	14	0	0
T140	0	8	0	0
T141	0	17	0	0
T152	0	1	0	0
T153	54168	0	0	0
T154	3125	0	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25349625	827	0	0
T18	9180	0	0	0
T27	320993	5	0	0
T28	3747	0	0	0
T29	18571	0	0	0
T30	1234	0	0	0
T31	278381	0	0	0
T32	4458	0	0	0
T81	0	4	0	0
T82	0	6	0	0
T90	0	11	0	0
T96	1349	0	0	0
T136	0	1	0	0
T137	0	9	0	0
T139	0	9	0	0
T140	0	16	0	0
T141	0	8	0	0
T152	0	3	0	0
T153	54168	0	0	0
T154	3125	0	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25349625	1597	0	0
T18	9180	0	0	0
T27	320993	12	0	0
T28	3747	0	0	0
T29	18571	0	0	0
T30	1234	0	0	0
T31	278381	0	0	0
T32	4458	0	0	0
T81	0	1	0	0
T82	0	5	0	0
T90	0	13	0	0
T96	1349	0	0	0
T136	0	5	0	0
T137	0	8	0	0
T139	0	1	0	0
T140	0	9	0	0
T141	0	8	0	0
T142	0	2	0	0
T153	54168	0	0	0
T154	3125	0	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25349625	849	0	0
T18	9180	0	0	0
T27	320993	5	0	0
T28	3747	0	0	0
T29	18571	0	0	0
T30	1234	0	0	0
T31	278381	0	0	0
T32	4458	0	0	0
T81	0	9	0	0
T82	0	13	0	0
T90	0	12	0	0
T96	1349	0	0	0
T137	0	2	0	0
T139	0	10	0	0
T140	0	18	0	0
T141	0	4	0	0
T142	0	8	0	0
T152	0	11	0	0
T153	54168	0	0	0
T154	3125	0	0	0