Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	74387949	152141	0	0
StatusRise_A	74387949	169731	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74387949	152141	0	0
T1	1246347	2003	0	0
T2	29070	28	0	0
T3	14391	15	0	0
T4	3402	6	0	0
T5	16755	18	0	0
T6	844065	2467	0	0
T7	75978	218	0	0
T8	36375	67	0	0
T9	10836	13	0	0
T10	45813	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74387949	169731	0	0
T1	1246347	2218	0	0
T2	29070	31	0	0
T3	14391	21	0	0
T4	3402	9	0	0
T5	16755	24	0	0
T6	844065	2744	0	0
T7	75978	223	0	0
T8	36375	73	0	0
T9	10836	15	0	0
T10	45813	6	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	24795983	56361	0	0
StatusRise_A	24795983	62747	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24795983	56361	0	0
T1	415449	722	0	0
T2	9690	10	0	0
T3	4797	5	0	0
T4	1134	2	0	0
T5	5585	6	0	0
T6	281355	920	0	0
T7	25326	85	0	0
T8	12125	26	0	0
T9	3612	5	0	0
T10	15271	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24795983	62747	0	0
T1	415449	800	0	0
T2	9690	11	0	0
T3	4797	7	0	0
T4	1134	3	0	0
T5	5585	8	0	0
T6	281355	1022	0	0
T7	25326	87	0	0
T8	12125	28	0	0
T9	3612	6	0	0
T10	15271	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	24795983	56361	0	0
StatusRise_A	24795983	62747	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24795983	56361	0	0
T1	415449	722	0	0
T2	9690	10	0	0
T3	4797	5	0	0
T4	1134	2	0	0
T5	5585	6	0	0
T6	281355	920	0	0
T7	25326	85	0	0
T8	12125	26	0	0
T9	3612	5	0	0
T10	15271	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24795983	62747	0	0
T1	415449	800	0	0
T2	9690	11	0	0
T3	4797	7	0	0
T4	1134	3	0	0
T5	5585	8	0	0
T6	281355	1022	0	0
T7	25326	87	0	0
T8	12125	28	0	0
T9	3612	6	0	0
T10	15271	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	24795983	39419	0	0
StatusRise_A	24795983	44237	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24795983	39419	0	0
T1	415449	559	0	0
T2	9690	8	0	0
T3	4797	5	0	0
T4	1134	2	0	0
T5	5585	6	0	0
T6	281355	627	0	0
T7	25326	48	0	0
T8	12125	15	0	0
T9	3612	3	0	0
T10	15271	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24795983	44237	0	0
T1	415449	618	0	0
T2	9690	9	0	0
T3	4797	7	0	0
T4	1134	3	0	0
T5	5585	8	0	0
T6	281355	700	0	0
T7	25326	49	0	0
T8	12125	17	0	0
T9	3612	3	0	0
T10	15271	2	0	0