Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	24796595	5601	0	0
EscTimeoutStoppedByClReset_A	24795983	3431971	0	0
EscTimeoutTriggersReset_A	5756549	326	0	0
RomAllowActiveState_A	24795983	62361	0	0
RomAllowCheckGoodState_A	24795983	62413	0	0
RomBlockActiveState_A	24795983	29185	0	0
RomBlockCheckGoodState_A	24795983	455314	0	0
RomIntgChkDisFalse_A	24795983	24069991	0	0
RomIntgChkDisTrue_A	24795983	185012	0	0
RstreqChkEsctimeout_A	24795983	4552	0	0
RstreqChkFsmterm_A	24795983	120	0	0
RstreqChkGlbesc_A	24795983	4552	0	0
RstreqChkMainpd_A	24795983	1023830	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24796595	5601	0	0
T10	15272	139	0	0
T11	656	1	0	0
T12	0	9	0	0
T13	213567	0	0	0
T20	21045	0	0	0
T33	153499	0	0	0
T34	22150	0	0	0
T55	4665	0	0	0
T74	14982	0	0	0
T75	6364	0	0	0
T91	2320	0	0	0
T155	0	116	0	0
T156	0	8	0	0
T157	0	230	0	0
T158	0	21	0	0
T159	0	94	0	0
T160	0	54	0	0
T161	0	4	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24795983	3431971	0	0
T1	415449	68413	0	0
T2	9690	1930	0	0
T3	4797	840	0	0
T4	1134	10	0	0
T5	5585	166	0	0
T6	281355	33559	0	0
T7	25326	3219	0	0
T8	12125	1673	0	0
T9	3612	518	0	0
T10	15271	12	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5756549	326	0	0
T10	232	2	0	0
T11	340	6	0	0
T12	0	3	0	0
T13	79472	0	0	0
T20	7654	0	0	0
T33	16421	0	0	0
T34	8151	0	0	0
T55	1794	0	0	0
T74	1695	0	0	0
T75	3501	0	0	0
T91	698	0	0	0
T155	0	2	0	0
T156	0	5	0	0
T157	0	3	0	0
T158	0	2	0	0
T162	0	4	0	0
T163	0	10	0	0
T164	0	3	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24795983	62361	0	0
T1	415449	800	0	0
T2	9690	11	0	0
T3	4797	7	0	0
T4	1134	3	0	0
T5	5585	8	0	0
T6	281355	1021	0	0
T7	25326	87	0	0
T8	12125	28	0	0
T9	3612	6	0	0
T10	15271	2	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24795983	62413	0	0
T1	415449	800	0	0
T2	9690	11	0	0
T3	4797	7	0	0
T4	1134	3	0	0
T5	5585	8	0	0
T6	281355	1021	0	0
T7	25326	87	0	0
T8	12125	28	0	0
T9	3612	6	0	0
T10	15271	2	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24795983	29185	0	0
T5	5585	934	0	0
T6	281355	0	0	0
T7	25326	2	0	0
T8	12125	0	0	0
T9	3612	0	0	0
T10	15271	0	0	0
T11	655	0	0	0
T13	213567	0	0	0
T20	21044	3	0	0
T21	0	300	0	0
T22	0	763	0	0
T29	0	13	0	0
T34	0	14	0	0
T74	14982	0	0	0
T77	0	8	0	0
T165	0	244	0	0
T166	0	140	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24795983	455314	0	0
T1	415449	1994	0	0
T2	9690	0	0	0
T3	4797	69	0	0
T4	1134	0	0	0
T5	5585	1077	0	0
T6	281355	3923	0	0
T7	25326	1304	0	0
T8	12125	321	0	0
T9	3612	0	0	0
T10	15271	0	0	0
T13	0	2202	0	0
T20	0	1322	0	0
T33	0	962	0	0
T34	0	1290	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24795983	24069991	0	0
T1	415449	409698	0	0
T2	9690	9610	0	0
T3	4797	4645	0	0
T4	1134	1049	0	0
T5	5585	5217	0	0
T6	281355	273623	0	0
T7	25326	25186	0	0
T8	12125	11965	0	0
T9	3612	3535	0	0
T10	15271	15188	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24795983	185012	0	0
T5	5585	192	0	0
T6	281355	0	0	0
T7	25326	0	0	0
T8	12125	0	0	0
T9	3612	0	0	0
T10	15271	0	0	0
T11	655	0	0	0
T13	213567	0	0	0
T20	21044	924	0	0
T21	0	483	0	0
T22	0	132	0	0
T29	0	549	0	0
T74	14982	0	0	0
T153	0	3952	0	0
T165	0	664	0	0
T166	0	208	0	0
T167	0	381	0	0
T168	0	1209	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24795983	4552	0	0
T1	415449	92	0	0
T2	9690	0	0	0
T3	4797	0	0	0
T4	1134	0	0	0
T5	5585	2	0	0
T6	281355	74	0	0
T7	25326	0	0	0
T8	12125	0	0	0
T9	3612	0	0	0
T10	15271	1	0	0
T11	0	1	0	0
T13	0	61	0	0
T33	0	30	0	0
T35	0	4	0	0
T36	0	9	0	0
T40	0	5	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24795983	120	0	0
T17	17340	40	0	0
T18	9180	20	0	0
T19	0	20	0	0
T23	0	20	0	0
T24	0	20	0	0
T25	2049	0	0	0
T26	1285	0	0	0
T27	320993	0	0	0
T28	3747	0	0	0
T29	18571	0	0	0
T30	1234	0	0	0
T31	278381	0	0	0
T32	4458	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24795983	4552	0	0
T1	415449	92	0	0
T2	9690	0	0	0
T3	4797	0	0	0
T4	1134	0	0	0
T5	5585	2	0	0
T6	281355	74	0	0
T7	25326	0	0	0
T8	12125	0	0	0
T9	3612	0	0	0
T10	15271	1	0	0
T11	0	1	0	0
T13	0	61	0	0
T33	0	30	0	0
T35	0	4	0	0
T36	0	9	0	0
T40	0	5	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24795983	1023830	0	0
T1	415449	17458	0	0
T2	9690	0	0	0
T3	4797	340	0	0
T4	1134	0	0	0
T5	5585	343	0	0
T6	281355	8230	0	0
T7	25326	1636	0	0
T8	12125	1262	0	0
T9	3612	0	0	0
T10	15271	0	0	0
T13	0	4487	0	0
T20	0	1680	0	0
T33	0	6914	0	0
T34	0	1597	0	0