Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7471 |
1 |
|
|
T4 |
3 |
|
T5 |
133 |
|
T38 |
5 |
auto[1] |
20925 |
1 |
|
|
T2 |
7 |
|
T3 |
1 |
|
T4 |
7 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12783 |
1 |
|
|
T2 |
5 |
|
T3 |
1 |
|
T4 |
6 |
auto[1] |
15613 |
1 |
|
|
T2 |
2 |
|
T4 |
4 |
|
T5 |
260 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13583 |
1 |
|
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
4 |
auto[1] |
14813 |
1 |
|
|
T2 |
6 |
|
T4 |
6 |
|
T5 |
255 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1781 |
1 |
|
|
T4 |
1 |
|
T5 |
35 |
|
T38 |
1 |
auto[0] |
auto[0] |
auto[1] |
1688 |
1 |
|
|
T5 |
31 |
|
T38 |
1 |
|
T39 |
2 |
auto[0] |
auto[1] |
auto[0] |
4884 |
1 |
|
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
2 |
auto[0] |
auto[1] |
auto[1] |
4430 |
1 |
|
|
T2 |
4 |
|
T4 |
3 |
|
T5 |
85 |
auto[1] |
auto[0] |
auto[0] |
1733 |
1 |
|
|
T5 |
25 |
|
T38 |
2 |
|
T73 |
1 |
auto[1] |
auto[0] |
auto[1] |
2269 |
1 |
|
|
T4 |
2 |
|
T5 |
42 |
|
T38 |
1 |
auto[1] |
auto[1] |
auto[0] |
5185 |
1 |
|
|
T4 |
1 |
|
T5 |
96 |
|
T10 |
13 |
auto[1] |
auto[1] |
auto[1] |
6426 |
1 |
|
|
T2 |
2 |
|
T4 |
1 |
|
T5 |
97 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7471 |
1 |
|
|
T4 |
3 |
|
T5 |
133 |
|
T38 |
5 |
auto[1] |
20925 |
1 |
|
|
T2 |
7 |
|
T3 |
1 |
|
T4 |
7 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12829 |
1 |
|
|
T2 |
5 |
|
T3 |
1 |
|
T4 |
4 |
auto[1] |
15567 |
1 |
|
|
T2 |
2 |
|
T4 |
6 |
|
T5 |
267 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13335 |
1 |
|
|
T2 |
2 |
|
T4 |
7 |
|
T5 |
216 |
auto[1] |
15061 |
1 |
|
|
T2 |
5 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1664 |
1 |
|
|
T4 |
1 |
|
T5 |
24 |
|
T38 |
3 |
auto[0] |
auto[0] |
auto[1] |
1795 |
1 |
|
|
T5 |
38 |
|
T38 |
1 |
|
T73 |
2 |
auto[0] |
auto[1] |
auto[0] |
4840 |
1 |
|
|
T2 |
1 |
|
T4 |
2 |
|
T5 |
84 |
auto[0] |
auto[1] |
auto[1] |
4530 |
1 |
|
|
T2 |
4 |
|
T3 |
1 |
|
T4 |
1 |
auto[1] |
auto[0] |
auto[0] |
1634 |
1 |
|
|
T5 |
27 |
|
T38 |
1 |
|
T73 |
1 |
auto[1] |
auto[0] |
auto[1] |
2378 |
1 |
|
|
T4 |
2 |
|
T5 |
44 |
|
T39 |
1 |
auto[1] |
auto[1] |
auto[0] |
5197 |
1 |
|
|
T2 |
1 |
|
T4 |
4 |
|
T5 |
81 |
auto[1] |
auto[1] |
auto[1] |
6358 |
1 |
|
|
T2 |
1 |
|
T5 |
115 |
|
T10 |
15 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7471 |
1 |
|
|
T4 |
3 |
|
T5 |
133 |
|
T38 |
5 |
auto[1] |
20925 |
1 |
|
|
T2 |
7 |
|
T3 |
1 |
|
T4 |
7 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12922 |
1 |
|
|
T2 |
3 |
|
T3 |
1 |
|
T4 |
5 |
auto[1] |
15474 |
1 |
|
|
T2 |
4 |
|
T4 |
5 |
|
T5 |
265 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13322 |
1 |
|
|
T2 |
2 |
|
T3 |
1 |
|
T4 |
2 |
auto[1] |
15074 |
1 |
|
|
T2 |
5 |
|
T4 |
8 |
|
T5 |
254 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1678 |
1 |
|
|
T4 |
1 |
|
T5 |
34 |
|
T38 |
2 |
auto[0] |
auto[0] |
auto[1] |
1800 |
1 |
|
|
T5 |
31 |
|
T38 |
2 |
|
T73 |
2 |
auto[0] |
auto[1] |
auto[0] |
4887 |
1 |
|
|
T2 |
2 |
|
T3 |
1 |
|
T4 |
1 |
auto[0] |
auto[1] |
auto[1] |
4557 |
1 |
|
|
T2 |
1 |
|
T4 |
3 |
|
T5 |
76 |
auto[1] |
auto[0] |
auto[0] |
1649 |
1 |
|
|
T5 |
28 |
|
T38 |
1 |
|
T73 |
2 |
auto[1] |
auto[0] |
auto[1] |
2344 |
1 |
|
|
T4 |
2 |
|
T5 |
40 |
|
T73 |
2 |
auto[1] |
auto[1] |
auto[0] |
5108 |
1 |
|
|
T5 |
90 |
|
T10 |
11 |
|
T38 |
2 |
auto[1] |
auto[1] |
auto[1] |
6373 |
1 |
|
|
T2 |
4 |
|
T4 |
3 |
|
T5 |
107 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7471 |
1 |
|
|
T4 |
3 |
|
T5 |
133 |
|
T38 |
5 |
auto[1] |
20925 |
1 |
|
|
T2 |
7 |
|
T3 |
1 |
|
T4 |
7 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12703 |
1 |
|
|
T2 |
3 |
|
T3 |
1 |
|
T4 |
1 |
auto[1] |
15693 |
1 |
|
|
T2 |
4 |
|
T4 |
9 |
|
T5 |
281 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13398 |
1 |
|
|
T2 |
5 |
|
T3 |
1 |
|
T4 |
3 |
auto[1] |
14998 |
1 |
|
|
T2 |
2 |
|
T4 |
7 |
|
T5 |
271 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1621 |
1 |
|
|
T4 |
1 |
|
T5 |
27 |
|
T73 |
1 |
auto[0] |
auto[0] |
auto[1] |
1765 |
1 |
|
|
T5 |
33 |
|
T73 |
1 |
|
T74 |
3 |
auto[0] |
auto[1] |
auto[0] |
4865 |
1 |
|
|
T2 |
2 |
|
T3 |
1 |
|
T5 |
73 |
auto[0] |
auto[1] |
auto[1] |
4452 |
1 |
|
|
T2 |
1 |
|
T5 |
66 |
|
T10 |
20 |
auto[1] |
auto[0] |
auto[0] |
1729 |
1 |
|
|
T4 |
1 |
|
T5 |
34 |
|
T38 |
1 |
auto[1] |
auto[0] |
auto[1] |
2356 |
1 |
|
|
T4 |
1 |
|
T5 |
39 |
|
T38 |
4 |
auto[1] |
auto[1] |
auto[0] |
5183 |
1 |
|
|
T2 |
3 |
|
T4 |
1 |
|
T5 |
75 |
auto[1] |
auto[1] |
auto[1] |
6425 |
1 |
|
|
T2 |
1 |
|
T4 |
6 |
|
T5 |
133 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7471 |
1 |
|
|
T4 |
3 |
|
T5 |
133 |
|
T38 |
5 |
auto[1] |
20925 |
1 |
|
|
T2 |
7 |
|
T3 |
1 |
|
T4 |
7 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12871 |
1 |
|
|
T2 |
6 |
|
T3 |
1 |
|
T4 |
5 |
auto[1] |
15525 |
1 |
|
|
T2 |
1 |
|
T4 |
5 |
|
T5 |
247 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13426 |
1 |
|
|
T2 |
2 |
|
T3 |
1 |
|
T4 |
5 |
auto[1] |
14970 |
1 |
|
|
T2 |
5 |
|
T4 |
5 |
|
T5 |
247 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1705 |
1 |
|
|
T4 |
2 |
|
T5 |
32 |
|
T38 |
1 |
auto[0] |
auto[0] |
auto[1] |
1741 |
1 |
|
|
T5 |
38 |
|
T38 |
1 |
|
T73 |
2 |
auto[0] |
auto[1] |
auto[0] |
4906 |
1 |
|
|
T2 |
2 |
|
T3 |
1 |
|
T4 |
1 |
auto[0] |
auto[1] |
auto[1] |
4519 |
1 |
|
|
T2 |
4 |
|
T4 |
2 |
|
T5 |
74 |
auto[1] |
auto[0] |
auto[0] |
1713 |
1 |
|
|
T5 |
28 |
|
T38 |
1 |
|
T39 |
1 |
auto[1] |
auto[0] |
auto[1] |
2312 |
1 |
|
|
T4 |
1 |
|
T5 |
35 |
|
T38 |
2 |
auto[1] |
auto[1] |
auto[0] |
5102 |
1 |
|
|
T4 |
2 |
|
T5 |
84 |
|
T10 |
13 |
auto[1] |
auto[1] |
auto[1] |
6398 |
1 |
|
|
T2 |
1 |
|
T4 |
2 |
|
T5 |
100 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7471 |
1 |
|
|
T4 |
3 |
|
T5 |
133 |
|
T38 |
5 |
auto[1] |
20925 |
1 |
|
|
T2 |
7 |
|
T3 |
1 |
|
T4 |
7 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12684 |
1 |
|
|
T2 |
5 |
|
T3 |
1 |
|
T4 |
5 |
auto[1] |
15712 |
1 |
|
|
T2 |
2 |
|
T4 |
5 |
|
T5 |
293 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13430 |
1 |
|
|
T2 |
2 |
|
T3 |
1 |
|
T4 |
7 |
auto[1] |
14966 |
1 |
|
|
T2 |
5 |
|
T4 |
3 |
|
T5 |
259 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1646 |
1 |
|
|
T4 |
1 |
|
T5 |
28 |
|
T74 |
2 |
auto[0] |
auto[0] |
auto[1] |
1705 |
1 |
|
|
T5 |
27 |
|
T73 |
3 |
|
T74 |
4 |
auto[0] |
auto[1] |
auto[0] |
4873 |
1 |
|
|
T2 |
2 |
|
T3 |
1 |
|
T4 |
2 |
auto[0] |
auto[1] |
auto[1] |
4460 |
1 |
|
|
T2 |
3 |
|
T4 |
2 |
|
T5 |
63 |
auto[1] |
auto[0] |
auto[0] |
1760 |
1 |
|
|
T4 |
1 |
|
T5 |
38 |
|
T38 |
1 |
auto[1] |
auto[0] |
auto[1] |
2360 |
1 |
|
|
T4 |
1 |
|
T5 |
40 |
|
T38 |
4 |
auto[1] |
auto[1] |
auto[0] |
5151 |
1 |
|
|
T4 |
3 |
|
T5 |
86 |
|
T10 |
6 |
auto[1] |
auto[1] |
auto[1] |
6441 |
1 |
|
|
T2 |
2 |
|
T5 |
129 |
|
T10 |
16 |