Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	537776	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

207818

1

T1

13

T2

39

T3

23

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	391610	1			T1	37		T2	67		T3	32
values[0x0]	176054	1			T1	14		T2	29		T3	5
values[0x1]	177930	1			T1	8		T2	36		T3	11

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	425670	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

319924

1

T1

28

T2

58

T3

28

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2649	1			T2	2		T4	1		T8	1
valid_sources[0x01]	3050	1			T4	1		T10	2		T38	1
valid_sources[0x02]	2208	1			T2	3		T4	1		T5	10
valid_sources[0x03]	2340	1			T5	15		T10	4		T73	1
valid_sources[0x04]	2258	1			T2	1		T5	5		T8	1
valid_sources[0x05]	2276	1			T5	5		T8	2		T10	1
valid_sources[0x06]	3165	1			T5	15		T10	4		T38	1
valid_sources[0x07]	2626	1			T4	1		T5	5		T10	1
valid_sources[0x08]	3985	1			T4	1		T5	5		T10	2
valid_sources[0x09]	2385	1			T10	1		T39	3		T34	7
valid_sources[0x0a]	3374	1			T8	2		T10	3		T38	2
valid_sources[0x0b]	3218	1			T5	15		T10	3		T38	2
valid_sources[0x0c]	2268	1			T5	5		T10	4		T39	2
valid_sources[0x0d]	2543	1			T10	2		T38	2		T73	2
valid_sources[0x0e]	2802	1			T4	2		T10	3		T73	2
valid_sources[0x0f]	2558	1			T4	1		T5	5		T10	2
valid_sources[0x10]	3190	1			T4	1		T5	5		T10	6
valid_sources[0x11]	2560	1			T4	2		T5	15		T8	2
valid_sources[0x12]	2304	1			T10	8		T38	1		T22	1
valid_sources[0x13]	3290	1			T4	1		T5	5		T10	5
valid_sources[0x14]	2277	1			T4	2		T5	10		T38	3
valid_sources[0x15]	2429	1			T5	5		T10	7		T38	2
valid_sources[0x16]	3300	1			T4	1		T5	5		T8	1
valid_sources[0x17]	2469	1			T2	1		T4	1		T5	10
valid_sources[0x18]	2348	1			T4	1		T5	10		T10	3
valid_sources[0x19]	2390	1			T2	2		T5	26		T10	1
valid_sources[0x1a]	2540	1			T4	1		T5	5		T10	4
valid_sources[0x1b]	2807	1			T4	1		T5	10		T10	9
valid_sources[0x1c]	2323	1			T4	1		T10	3		T13	14
valid_sources[0x1d]	3078	1			T2	1		T4	1		T5	10
valid_sources[0x1e]	3837	1			T4	1		T10	3		T182	1
valid_sources[0x1f]	2175	1			T34	3		T73	2		T35	1
valid_sources[0x20]	2270	1			T5	5		T10	3		T38	2
valid_sources[0x21]	3153	1			T4	1		T10	3		T182	1
valid_sources[0x22]	2385	1			T5	5		T10	2		T38	1
valid_sources[0x23]	2370	1			T2	1		T4	1		T5	5
valid_sources[0x24]	3657	1			T2	3		T10	4		T38	1
valid_sources[0x25]	2399	1			T4	2		T5	5		T10	5
valid_sources[0x26]	2892	1			T10	2		T38	1		T22	1
valid_sources[0x27]	2129	1			T10	3		T38	2		T75	4
valid_sources[0x28]	3883	1			T4	1		T5	10		T10	1
valid_sources[0x29]	2563	1			T2	1		T4	2		T10	1
valid_sources[0x2a]	3794	1			T4	1		T5	10		T8	2
valid_sources[0x2b]	2580	1			T2	1		T5	5		T10	8
valid_sources[0x2c]	3189	1			T4	1		T5	10		T10	5
valid_sources[0x2d]	2413	1			T10	5		T38	2		T39	9
valid_sources[0x2e]	6367	1			T5	5		T10	1		T73	2
valid_sources[0x2f]	2423	1			T5	5		T10	1		T38	2
valid_sources[0x30]	2689	1			T2	1		T4	1		T5	10
valid_sources[0x31]	2404	1			T2	5		T5	5		T10	5
valid_sources[0x32]	2564	1			T10	2		T73	1		T35	1
valid_sources[0x33]	2375	1			T4	2		T5	21		T10	3
valid_sources[0x34]	2443	1			T4	1		T8	7		T10	3
valid_sources[0x35]	3259	1			T4	2		T5	10		T8	2
valid_sources[0x36]	2791	1			T2	2		T5	15		T10	4
valid_sources[0x37]	2277	1			T4	1		T5	24		T10	1
valid_sources[0x38]	2359	1			T5	10		T10	2		T73	1
valid_sources[0x39]	2568	1			T5	10		T10	5		T38	1
valid_sources[0x3a]	2171	1			T10	5		T38	1		T22	3
valid_sources[0x3b]	3206	1			T5	5		T10	6		T38	3
valid_sources[0x3c]	2868	1			T4	1		T5	5		T10	2
valid_sources[0x3d]	2700	1			T4	1		T5	20		T10	7
valid_sources[0x3e]	3545	1			T2	3		T10	2		T182	2
valid_sources[0x3f]	2108	1			T2	1		T5	5		T10	2
valid_sources[0x40]	2265	1			T2	3		T5	5		T10	3
valid_sources[0x41]	2417	1			T10	1		T38	2		T73	1
valid_sources[0x42]	2572	1			T4	1		T5	5		T10	6
valid_sources[0x43]	3884	1			T2	1		T10	1		T38	1
valid_sources[0x44]	3789	1			T4	1		T5	5		T10	2
valid_sources[0x45]	2915	1			T5	5		T38	1		T22	2
valid_sources[0x46]	2216	1			T5	5		T10	7		T38	1
valid_sources[0x47]	2560	1			T4	2		T5	5		T10	2
valid_sources[0x48]	2358	1			T5	5		T10	7		T38	1
valid_sources[0x49]	2322	1			T10	3		T38	1		T73	1
valid_sources[0x4a]	2378	1			T10	2		T22	2		T34	4
valid_sources[0x4b]	4384	1			T5	10		T10	1		T34	4
valid_sources[0x4c]	3735	1			T4	1		T10	10		T38	2
valid_sources[0x4d]	2952	1			T2	1		T10	7		T38	3
valid_sources[0x4e]	2641	1			T5	20		T8	1		T10	3
valid_sources[0x4f]	2342	1			T10	6		T34	3		T73	2
valid_sources[0x50]	2262	1			T2	2		T5	15		T10	5
valid_sources[0x51]	2420	1			T2	1		T4	2		T10	1
valid_sources[0x52]	2501	1			T5	10		T10	5		T38	1
valid_sources[0x53]	2354	1			T4	1		T5	5		T10	3
valid_sources[0x54]	16325	1			T5	13998		T8	1		T10	1
valid_sources[0x55]	2225	1			T2	1		T5	5		T10	6
valid_sources[0x56]	2648	1			T10	1		T34	1		T13	14
valid_sources[0x57]	2243	1			T2	2		T5	5		T10	3
valid_sources[0x58]	2938	1			T2	1		T4	1		T5	5
valid_sources[0x59]	2296	1			T2	1		T5	5		T10	2
valid_sources[0x5a]	2066	1			T4	1		T10	3		T38	2
valid_sources[0x5b]	3429	1			T10	7		T38	1		T75	3
valid_sources[0x5c]	2723	1			T10	1		T38	2		T22	1
valid_sources[0x5d]	3324	1			T10	2		T22	1		T34	1
valid_sources[0x5e]	2538	1			T2	2		T3	48		T4	1
valid_sources[0x5f]	2297	1			T2	1		T5	6		T10	4
valid_sources[0x60]	2442	1			T2	2		T4	2		T10	2
valid_sources[0x61]	2367	1			T10	8		T38	2		T182	2
valid_sources[0x62]	10141	1			T5	10		T10	2		T38	2
valid_sources[0x63]	2401	1			T2	1		T5	5		T10	3
valid_sources[0x64]	3616	1			T4	1		T5	5		T10	2
valid_sources[0x65]	2456	1			T2	3		T4	1		T5	5
valid_sources[0x66]	2377	1			T2	2		T4	3		T10	2
valid_sources[0x67]	2203	1			T4	1		T5	10		T10	11
valid_sources[0x68]	2608	1			T4	1		T10	3		T34	2
valid_sources[0x69]	3103	1			T5	15		T10	4		T39	1
valid_sources[0x6a]	3592	1			T4	1		T5	5		T10	7
valid_sources[0x6b]	2756	1			T4	1		T10	4		T73	1
valid_sources[0x6c]	3568	1			T2	1		T8	1		T10	4
valid_sources[0x6d]	2802	1			T4	1		T5	5		T10	13
valid_sources[0x6e]	2668	1			T2	2		T5	5		T10	3
valid_sources[0x6f]	4651	1			T5	5		T10	4		T38	1
valid_sources[0x70]	2208	1			T5	5		T10	4		T38	2
valid_sources[0x71]	3251	1			T5	5		T10	2		T38	1
valid_sources[0x72]	2714	1			T2	2		T4	1		T5	10
valid_sources[0x73]	2368	1			T4	1		T5	5		T10	1
valid_sources[0x74]	2416	1			T4	1		T10	5		T38	2
valid_sources[0x75]	2476	1			T9	1		T10	4		T38	1
valid_sources[0x76]	2270	1			T5	10		T10	2		T73	1
valid_sources[0x77]	2305	1			T4	1		T5	10		T10	1
valid_sources[0x78]	2609	1			T5	10		T22	3		T182	2
valid_sources[0x79]	2475	1			T10	2		T38	2		T34	1
valid_sources[0x7a]	2485	1			T5	10		T10	5		T38	1
valid_sources[0x7b]	2439	1			T2	3		T5	5		T10	2
valid_sources[0x7c]	2446	1			T1	59		T8	1		T10	2
valid_sources[0x7d]	3482	1			T2	3		T4	1		T5	10
valid_sources[0x7e]	2356	1			T2	2		T10	6		T38	3
valid_sources[0x7f]	2281	1			T2	1		T5	20		T10	1
valid_sources[0x80]	2207	1			T2	1		T5	5		T10	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

106297

1

T1

7

T2

20

T3

16

values[0x0]

all_enables

biggest_size

65592

1

T1

4

T2

11

T3

3

values[0x1]

all_enables

biggest_size

35929

1

T1

2

T2

8

T3

4