SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34947 | 1 | T10 | 320 | T72 | 314 | T92 | 414 | ||||
others[1] | 35202 | 1 | T10 | 297 | T21 | 1 | T72 | 304 | ||||
others[2] | 34939 | 1 | T10 | 317 | T21 | 1 | T72 | 266 | ||||
others[3] | 58413 | 1 | T1 | 1 | T10 | 464 | T21 | 1 | ||||
false | 20353 | 1 | T1 | 4 | T2 | 14 | T5 | 390 | ||||
true | 30698 | 1 | T1 | 4 | T2 | 16 | T3 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34983 | 1 | T1 | 1 | T10 | 316 | T72 | 300 | ||||
others[1] | 35176 | 1 | T10 | 295 | T72 | 293 | T92 | 413 | ||||
others[2] | 34866 | 1 | T10 | 288 | T44 | 1 | T72 | 281 | ||||
others[3] | 58557 | 1 | T10 | 500 | T72 | 527 | T92 | 653 | ||||
false | 12782 | 1 | T1 | 3 | T2 | 7 | T5 | 195 | ||||
true | 23178 | 1 | T1 | 5 | T2 | 9 | T3 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 696 | 1 | T5 | 9 | T182 | 6 | T13 | 4 | ||||
others[1] | 704 | 1 | T5 | 8 | T35 | 3 | T182 | 8 | ||||
others[2] | 711 | 1 | T5 | 13 | T22 | 1 | T35 | 1 | ||||
others[3] | 1168 | 1 | T1 | 2 | T5 | 12 | T22 | 2 | ||||
false | 14187 | 1 | T1 | 5 | T2 | 2 | T3 | 5 | ||||
true | 4189 | 1 | T1 | 2 | T5 | 89 | T22 | 5 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |