Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	26168902	14144	0	0
intr_enable_rd_A	26168902	33761	0	0
reset_en_rd_A	26168902	2420	0	0
reset_en_regwen_rd_A	26168902	1965	0	0
wake_info_capture_dis_rd_A	26168902	1934	0	0
wakeup_en_rd_A	26168902	3176	0	0
wakeup_en_regwen_rd_A	26168902	2065	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26168902	14144	0	0
T5	595483	98	0	0
T6	2390	0	0	0
T7	1818	0	0	0
T8	1437	0	0	0
T9	3061	0	0	0
T10	52562	0	0	0
T11	660	0	0	0
T13	0	11	0	0
T14	0	112	0	0
T22	8314	0	0	0
T38	6277	0	0	0
T39	1098	0	0	0
T47	0	87	0	0
T82	0	33	0	0
T87	0	3	0	0
T88	0	3	0	0
T89	0	4	0	0
T129	0	20	0	0
T130	0	14	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26168902	33761	0	0
T4	10080	39	0	0
T5	595483	0	0	0
T6	2390	0	0	0
T7	1818	0	0	0
T8	1437	0	0	0
T9	3061	0	0	0
T10	52562	0	0	0
T11	660	0	0	0
T21	0	20	0	0
T22	8314	0	0	0
T38	6277	0	0	0
T71	0	10	0	0
T77	0	12	0	0
T78	0	48	0	0
T80	0	29	0	0
T81	0	104	0	0
T94	0	14	0	0
T131	0	35	0	0
T132	0	177	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26168902	2420	0	0
T50	0	48	0	0
T51	0	6	0	0
T54	0	51	0	0
T119	0	25	0	0
T133	445273	2	0	0
T134	0	2	0	0
T135	0	8	0	0
T136	0	5	0	0
T137	0	6	0	0
T138	0	16	0	0
T139	1627	0	0	0
T140	3058	0	0	0
T141	13079	0	0	0
T142	7464	0	0	0
T143	3017	0	0	0
T144	1480	0	0	0
T145	3611	0	0	0
T146	1657	0	0	0
T147	27344	0	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26168902	1965	0	0
T18	8652	0	0	0
T25	15629	0	0	0
T26	2261	0	0	0
T27	16522	0	0	0
T28	4550	0	0	0
T29	1415	0	0	0
T30	1345	0	0	0
T31	7088	0	0	0
T50	0	15	0	0
T51	0	2	0	0
T54	0	42	0	0
T87	194786	7	0	0
T119	0	10	0	0
T134	0	9	0	0
T135	0	3	0	0
T136	0	6	0	0
T138	0	8	0	0
T148	0	5	0	0
T149	3020	0	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26168902	1934	0	0
T50	0	22	0	0
T51	0	3	0	0
T54	0	75	0	0
T105	0	12	0	0
T119	0	22	0	0
T133	445273	1	0	0
T134	0	6	0	0
T135	0	11	0	0
T138	0	5	0	0
T139	1627	0	0	0
T140	3058	0	0	0
T141	13079	0	0	0
T142	7464	0	0	0
T143	3017	0	0	0
T144	1480	0	0	0
T145	3611	0	0	0
T146	1657	0	0	0
T147	27344	0	0	0
T150	0	4	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26168902	3176	0	0
T51	0	6	0	0
T54	0	21	0	0
T82	156803	0	0	0
T97	2209	0	0	0
T130	428559	6	0	0
T133	0	6	0	0
T134	0	16	0	0
T135	0	7	0	0
T136	0	1	0	0
T137	0	4	0	0
T138	0	7	0	0
T150	0	5	0	0
T151	1974	0	0	0
T152	1389	0	0	0
T153	1314	0	0	0
T154	2421	0	0	0
T155	7300	0	0	0
T156	23140	0	0	0
T157	1228	0	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26168902	2065	0	0
T51	0	12	0	0
T54	0	34	0	0
T82	156803	0	0	0
T97	2209	0	0	0
T119	0	41	0	0
T130	428559	2	0	0
T133	0	2	0	0
T134	0	14	0	0
T135	0	5	0	0
T136	0	2	0	0
T137	0	4	0	0
T138	0	1	0	0
T151	1974	0	0	0
T152	1389	0	0	0
T153	1314	0	0	0
T154	2421	0	0	0
T155	7300	0	0	0
T156	23140	0	0	0
T157	1228	0	0	0