Unified Coverage Report :: Module :: pwrmgr_slow_fsm

Module : pwrmgr_slow_fsm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.41	100.00	97.06		100.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_pwrmgr_component_0.1/rtl/pwrmgr_slow_fsm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_slow_fsm	99.41	100.00	97.06		100.00	100.00	100.00

---

Module Instance : tb.dut.u_slow_fsm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.41	100.00	97.06		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.41	100.00	97.06		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_main_pok_sync	100.00	100.00				100.00
u_state_regs	100.00	100.00				100.00	100.00
u_usb_clk_en	100.00	100.00				100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_slow_fsm

	Line No.	Total	Covered	Percent
TOTAL		110	110	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
ALWAYS	110	23	23	100.00
ALWAYS	138	3	3	100.00
ALWAYS	141	49	49	100.00
ALWAYS	268	3	3	100.00
ALWAYS	288	6	6	100.00
CONT_ASSIGN	302	1	1	100.00
ALWAYS	305	5	5	100.00
CONT_ASSIGN	314	1	1	100.00
CONT_ASSIGN	315	1	1	100.00
CONT_ASSIGN	316	1	1	100.00
CONT_ASSIGN	317	1	1	100.00
CONT_ASSIGN	318	1	1	100.00
CONT_ASSIGN	320	1	1	100.00
CONT_ASSIGN	321	1	1	100.00
CONT_ASSIGN	335	1	1	100.00
CONT_ASSIGN	337	1	1	100.00
CONT_ASSIGN	338	1	1	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	349	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_pwrmgr_component_0.1/rtl/pwrmgr_slow_fsm.sv' or '../src/lowrisc_ip_pwrmgr_component_0.1/rtl/pwrmgr_slow_fsm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
75	1	1
85	1	1
90	1	1
91	1	1
95	1	1
105	1	1
106	1	1
107	1	1
110	1	1
111	1	1
112	1	1
113	1	1
114	1	1
115	1	1
116	1	1
117	1	1
118	1	1
119	1	1
120	1	1
121	1	1
123	1	1
124	1	1
125	1	1
126	1	1
127	1	1
128	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
138	3	3
141	1	1
142	1	1
143	1	1
144	1	1
145	1	1
146	1	1
148	1	1
149	1	1
150	1	1
152	1	1
154	1	1
156	1	1
159	1	1
160	1	1
166	1	1
167	1	1
168	1	1
169	1	1
			MISSING_ELSE
174	1	1
176	1	1
177	1	1
178	1	1
179	1	1
			MISSING_ELSE
184	1	1
185	1	1
189	1	1
191	1	1
192	1	1
			MISSING_ELSE
197	1	1
198	1	1
202	1	1
203	1	1
204	1	1
			MISSING_ELSE
211	1	1
213	1	1
214	1	1
			MISSING_ELSE
219	1	1
220	1	1
222	1	1
223	1	1
224	1	1
			MISSING_ELSE
229	1	1
231	1	1
232	1	1
			MISSING_ELSE
238	1	1
239	1	1
243	1	1
247	1	1
248	1	1
			MISSING_ELSE
268	1	1
269	1	1
271	1	1
288	1	1
289	1	1
290	1	1
291	1	1
292	1	1
293	1	1
			MISSING_ELSE
302	1	1
305	1	1
306	1	1
307	1	1
308	1	1
310	1	1
314	1	1
315	1	1
316	1	1
317	1	1
318	1	1
320	1	1
321	1	1
335	1	1
337	1	1
338	1	1
339	1	1
349	1	1

---

Cond Coverage for Module : pwrmgr_slow_fsm

	Total	Covered	Percent
Conditions	68	66	97.06
Logical	68	66	97.06
Non-Logical	0	0
Event	0	0

 LINE       75
 EXPRESSION (ast_i.core_clk_val & ast_i.io_clk_val & (((~usb_clk_en_active_i)) | ast_i.usb_clk_val))
             ---------1--------   --------2-------   -----------------------3----------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T4,T5
1	1	0	Covered	T2,T3,T4
1	1	1	Covered	T1,T2,T3

 LINE       75
 SUB-EXPRESSION (((~usb_clk_en_active_i)) | ast_i.usb_clk_val)
                 ------------1-----------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5

 LINE       85
 EXPRESSION (main_pd_ni & usb_clk_en_lp_i)
             -----1----   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T8

 LINE       90
 EXPRESSION (main_pd_ni & core_clk_en_i)
             -----1----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

 LINE       91
 EXPRESSION (main_pd_ni & io_clk_en_i)
             -----1----   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

 LINE       95
 EXPRESSION ((core_clk_en | ((~ast_i.core_clk_val))) & (io_clk_en | ((~ast_i.io_clk_val))) & (usb_clk_en_lp | ((~ast_i.usb_clk_val))))
             -------------------1-------------------   -----------------2-----------------   --------------------3-------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T2,T4,T5
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       95
 SUB-EXPRESSION (core_clk_en | ((~ast_i.core_clk_val)))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5

 LINE       95
 SUB-EXPRESSION (io_clk_en | ((~ast_i.io_clk_val)))
                 ----1----   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5

 LINE       95
 SUB-EXPRESSION (usb_clk_en_lp | ((~ast_i.usb_clk_val)))
                 ------1------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T8

 LINE       105
 EXPRESSION (fsm_invalid_q | clk_active | core_clk_en)
             ------1------   -----2----   -----3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T2,T4,T5
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T18,T19,T20

 LINE       106
 EXPRESSION (fsm_invalid_q | clk_active | io_clk_en)
             ------1------   -----2----   ----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T2,T4,T5
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T18,T19,T20

 LINE       107
 EXPRESSION (fsm_invalid_q | (clk_active ? usb_clk_en_active_i : usb_clk_en_lp))
             ------1------   -------------------------2------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T18,T19,T20

 LINE       107
 SUB-EXPRESSION (clk_active ? usb_clk_en_active_i : usb_clk_en_lp)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       166
 EXPRESSION (wakeup_i || reset_req_i)
             ----1---    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Covered	T2,T5,T10
1	0	Covered	T2,T4,T5

 LINE       169
 EXPRESSION (reset_req_i ? Reset : Wake)
             -----1-----

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T2,T5,T10

 LINE       202
 EXPRESSION (ack_pwrup_i && ((!req_pwrdn_i)))
             -----1-----    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       213
 EXPRESSION (req_pwrdn_i && ((!ack_pwrup_i)))
             -----1-----    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T4,T5

 LINE       247
 EXPRESSION (((!main_pok_st)) | main_pd_ni)
             --------1-------   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5

 LINE       290
 EXPRESSION (((!pd_nd)) && mon_main_pok)
             -----1----    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       302
 EXPRESSION (mon_main_pok & ((~main_pok_st)))
             ------1-----   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       310
 EXPRESSION (rst_req_o | pwr_rst_req)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T5

 LINE       327
 EXPRESSION (usb_clk_en_q | usb_ip_clk_status_i)
             ------1-----   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T10
1	0	Covered	T1,T2,T3

---

FSM Coverage for Module : pwrmgr_slow_fsm

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	11	11	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
SlowPwrStateAckPwrDn	214	Covered	T2,T4,T5
SlowPwrStateClocksOff	224	Covered	T2,T4,T5
SlowPwrStateClocksOn	185	Covered	T1,T2,T3
SlowPwrStateIdle	204	Covered	T1,T2,T3
SlowPwrStateLowPower	248	Covered	T2,T4,T5
SlowPwrStateMainPowerOff	239	Covered	T2,T4,T5
SlowPwrStateMainPowerOn	159	Covered	T1,T2,T3
SlowPwrStatePwrClampOff	179	Covered	T1,T2,T3
SlowPwrStatePwrClampOn	232	Covered	T2,T4,T5
SlowPwrStateReqPwrUp	192	Covered	T1,T2,T3
SlowPwrStateReset	158	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
SlowPwrStateAckPwrDn->SlowPwrStateClocksOff	224	Covered	T2,T4,T5
SlowPwrStateClocksOff->SlowPwrStatePwrClampOn	232	Covered	T2,T4,T5
SlowPwrStateClocksOn->SlowPwrStateReqPwrUp	192	Covered	T1,T2,T3
SlowPwrStateIdle->SlowPwrStateAckPwrDn	214	Covered	T2,T4,T5
SlowPwrStateLowPower->SlowPwrStateMainPowerOn	167	Covered	T2,T4,T5
SlowPwrStateMainPowerOff->SlowPwrStateLowPower	248	Covered	T2,T4,T5
SlowPwrStateMainPowerOn->SlowPwrStatePwrClampOff	179	Covered	T1,T2,T3
SlowPwrStatePwrClampOff->SlowPwrStateClocksOn	185	Covered	T1,T2,T3
SlowPwrStatePwrClampOn->SlowPwrStateMainPowerOff	239	Covered	T2,T4,T5
SlowPwrStateReqPwrUp->SlowPwrStateIdle	204	Covered	T1,T2,T3
SlowPwrStateReset->SlowPwrStateMainPowerOn	159	Covered	T1,T2,T3

---

Branch Coverage for Module : pwrmgr_slow_fsm

	Line No.	Total	Covered	Percent
Branches		34	34	100.00
IF	110	2	2	100.00
IF	138	2	2	100.00
CASE	156	21	21	100.00
IF	268	2	2	100.00
IF	288	4	4	100.00
IF	305	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_pwrmgr_component_0.1/rtl/pwrmgr_slow_fsm.sv' or '../src/lowrisc_ip_pwrmgr_component_0.1/rtl/pwrmgr_slow_fsm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	110	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	156	case (state_q)
-2-:	166	if ((wakeup_i || reset_req_i))
-3-:	169	(reset_req_i) ? 
-4-:	176	if (main_pok_st)
-5-:	191	if (all_clks_valid)
-6-:	202	if ((ack_pwrup_i && (!req_pwrdn_i)))
-7-:	213	if ((req_pwrdn_i && (!ack_pwrup_i)))
-8-:	222	if ((!req_pwrdn_i))
-9-:	229	if (all_clks_invalid)
-10-:	247	if (((!main_pok_st) | main_pd_ni))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	Status	Tests
SlowPwrStateReset	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
SlowPwrStateLowPower	1	1	-	-	-	-	-	-	-	Covered	T2,T5,T10
SlowPwrStateLowPower	1	0	-	-	-	-	-	-	-	Covered	T2,T4,T5
SlowPwrStateLowPower	0	-	-	-	-	-	-	-	-	Covered	T2,T4,T5
SlowPwrStateMainPowerOn	-	-	1	-	-	-	-	-	-	Covered	T1,T2,T3
SlowPwrStateMainPowerOn	-	-	0	-	-	-	-	-	-	Covered	T1,T2,T3
SlowPwrStatePwrClampOff	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
SlowPwrStateClocksOn	-	-	-	1	-	-	-	-	-	Covered	T1,T2,T3
SlowPwrStateClocksOn	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T3
SlowPwrStateReqPwrUp	-	-	-	-	1	-	-	-	-	Covered	T1,T2,T3
SlowPwrStateReqPwrUp	-	-	-	-	0	-	-	-	-	Covered	T1,T2,T3
SlowPwrStateIdle	-	-	-	-	-	1	-	-	-	Covered	T2,T4,T5
SlowPwrStateIdle	-	-	-	-	-	0	-	-	-	Covered	T1,T2,T3
SlowPwrStateAckPwrDn	-	-	-	-	-	-	1	-	-	Covered	T2,T4,T5
SlowPwrStateAckPwrDn	-	-	-	-	-	-	0	-	-	Covered	T2,T4,T5
SlowPwrStateClocksOff	-	-	-	-	-	-	-	1	-	Covered	T2,T4,T5
SlowPwrStateClocksOff	-	-	-	-	-	-	-	0	-	Covered	T2,T4,T5
SlowPwrStatePwrClampOn	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T5
SlowPwrStateMainPowerOff	-	-	-	-	-	-	-	-	1	Covered	T2,T4,T5
SlowPwrStateMainPowerOff	-	-	-	-	-	-	-	-	0	Covered	T2,T4,T5
default	-	-	-	-	-	-	-	-	-	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	268	if ((!rst_main_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	288	if ((!rst_ni))
-2-:	290	if (((!pd_nd) && mon_main_pok))
-3-:	292	if (set_main_pok)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T4,T5
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))
-2-:	307	if (clr_req_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_slow_fsm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IntRstReq_A	685312	675414	0	0
u_state_regs_A	5027937	4991499	0	0

IntRstReq_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685312	675414	0	0
T1	147	142	0	0
T2	86	81	0	0
T3	315	290	0	0
T4	1079	1074	0	0
T5	136	126	0	0
T6	213	203	0	0
T7	805	775	0	0
T8	513	488	0	0
T9	320	290	0	0
T10	97	92	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5027937	4991499	0	0
T1	1150	1145	0	0
T2	1045	1035	0	0
T3	315	290	0	0
T4	1079	1074	0	0
T5	64957	64281	0	0
T6	213	203	0	0
T7	805	775	0	0
T8	513	488	0	0
T9	320	290	0	0
T10	5562	5552	0	0