Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	76580625	151198	0	0
StatusRise_A	76580625	168964	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	76580625	151198	0	0
T1	4350	15	0	0
T2	29118	34	0	0
T3	9030	12	0	0
T4	30240	27	0	0
T5	1786449	3115	0	0
T6	7170	3	0	0
T7	5454	0	0	0
T8	4311	12	0	0
T9	9183	0	0	0
T10	157686	211	0	0
T11	0	3	0	0
T38	0	47	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	76580625	168964	0	0
T1	4350	18	0	0
T2	29118	39	0	0
T3	9030	15	0	0
T4	30240	30	0	0
T5	1786449	3485	0	0
T6	7170	9	0	0
T7	5454	18	0	0
T8	4311	15	0	0
T9	9183	18	0	0
T10	157686	216	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	25526875	56172	0	0
StatusRise_A	25526875	62588	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25526875	56172	0	0
T1	1450	5	0	0
T2	9706	12	0	0
T3	3010	4	0	0
T4	10080	10	0	0
T5	595483	1139	0	0
T6	2390	1	0	0
T7	1818	0	0	0
T8	1437	4	0	0
T9	3061	0	0	0
T10	52562	84	0	0
T11	0	1	0	0
T38	0	18	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25526875	62588	0	0
T1	1450	6	0	0
T2	9706	14	0	0
T3	3010	5	0	0
T4	10080	11	0	0
T5	595483	1274	0	0
T6	2390	3	0	0
T7	1818	6	0	0
T8	1437	5	0	0
T9	3061	6	0	0
T10	52562	86	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	25526875	56172	0	0
StatusRise_A	25526875	62588	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25526875	56172	0	0
T1	1450	5	0	0
T2	9706	12	0	0
T3	3010	4	0	0
T4	10080	10	0	0
T5	595483	1139	0	0
T6	2390	1	0	0
T7	1818	0	0	0
T8	1437	4	0	0
T9	3061	0	0	0
T10	52562	84	0	0
T11	0	1	0	0
T38	0	18	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25526875	62588	0	0
T1	1450	6	0	0
T2	9706	14	0	0
T3	3010	5	0	0
T4	10080	11	0	0
T5	595483	1274	0	0
T6	2390	3	0	0
T7	1818	6	0	0
T8	1437	5	0	0
T9	3061	6	0	0
T10	52562	86	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	25526875	38854	0	0
StatusRise_A	25526875	43788	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25526875	38854	0	0
T1	1450	5	0	0
T2	9706	10	0	0
T3	3010	4	0	0
T4	10080	7	0	0
T5	595483	837	0	0
T6	2390	1	0	0
T7	1818	0	0	0
T8	1437	4	0	0
T9	3061	0	0	0
T10	52562	43	0	0
T11	0	1	0	0
T38	0	11	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25526875	43788	0	0
T1	1450	6	0	0
T2	9706	11	0	0
T3	3010	5	0	0
T4	10080	8	0	0
T5	595483	937	0	0
T6	2390	3	0	0
T7	1818	6	0	0
T8	1437	5	0	0
T9	3061	6	0	0
T10	52562	44	0	0