Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	25527470	6082	0	0
EscTimeoutStoppedByClReset_A	25526875	3604811	0	0
EscTimeoutTriggersReset_A	5027937	312	0	0
RomAllowActiveState_A	25526875	62196	0	0
RomAllowCheckGoodState_A	25526875	62246	0	0
RomBlockActiveState_A	25526875	28390	0	0
RomBlockCheckGoodState_A	25526875	441164	0	0
RomIntgChkDisFalse_A	25526875	24894198	0	0
RomIntgChkDisTrue_A	25526875	86561	0	0
RstreqChkEsctimeout_A	25526875	4586	0	0
RstreqChkFsmterm_A	25526875	140	0	0
RstreqChkGlbesc_A	25526875	4586	0	0
RstreqChkMainpd_A	25526875	1029823	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25527470	6082	0	0
T11	661	5	0	0
T15	1244	0	0	0
T16	1323	0	0	0
T22	8315	0	0	0
T26	0	34	0	0
T34	4892	0	0	0
T35	4710	0	0	0
T38	6278	0	0	0
T39	1098	0	0	0
T73	13618	0	0	0
T74	4126	0	0	0
T158	0	122	0	0
T159	0	32	0	0
T160	0	13	0	0
T161	0	81	0	0
T162	0	2	0	0
T163	0	56	0	0
T164	0	87	0	0
T165	0	4	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25526875	3604811	0	0
T1	1450	73	0	0
T2	9706	2239	0	0
T3	3010	71	0	0
T4	10080	1931	0	0
T5	595483	99743	0	0
T6	2390	20	0	0
T7	1818	60	0	0
T8	1437	52	0	0
T9	3061	19	0	0
T10	52562	10442	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5027937	312	0	0
T6	213	3	0	0
T7	805	0	0	0
T8	513	0	0	0
T9	320	0	0	0
T10	5562	0	0	0
T11	345	7	0	0
T12	0	4	0	0
T15	460	0	0	0
T22	784	0	0	0
T38	2412	0	0	0
T39	854	0	0	0
T158	0	3	0	0
T159	0	2	0	0
T160	0	2	0	0
T161	0	2	0	0
T162	0	4	0	0
T166	0	3	0	0
T167	0	2	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25526875	62196	0	0
T1	1450	6	0	0
T2	9706	14	0	0
T3	3010	5	0	0
T4	10080	11	0	0
T5	595483	1274	0	0
T6	2390	3	0	0
T7	1818	6	0	0
T8	1437	5	0	0
T9	3061	6	0	0
T10	52562	86	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25526875	62246	0	0
T1	1450	6	0	0
T2	9706	14	0	0
T3	3010	5	0	0
T4	10080	11	0	0
T5	595483	1274	0	0
T6	2390	3	0	0
T7	1818	6	0	0
T8	1437	5	0	0
T9	3061	6	0	0
T10	52562	86	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25526875	28390	0	0
T1	1450	47	0	0
T2	9706	0	0	0
T3	3010	0	0	0
T4	10080	0	0	0
T5	595483	0	0	0
T6	2390	0	0	0
T7	1818	0	0	0
T8	1437	0	0	0
T9	3061	0	0	0
T10	52562	0	0	0
T21	0	1199	0	0
T37	0	624	0	0
T44	0	123	0	0
T93	0	40	0	0
T149	0	354	0	0
T168	0	359	0	0
T169	0	739	0	0
T170	0	4	0	0
T171	0	22	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25526875	441164	0	0
T2	9706	161	0	0
T3	3010	0	0	0
T4	10080	0	0	0
T5	595483	4472	0	0
T6	2390	0	0	0
T7	1818	0	0	0
T8	1437	0	0	0
T9	3061	0	0	0
T10	52562	3984	0	0
T11	660	0	0	0
T13	0	1171	0	0
T14	0	2870	0	0
T21	0	994	0	0
T34	0	230	0	0
T44	0	17	0	0
T72	0	4097	0	0
T92	0	1263	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25526875	24894198	0	0
T1	1450	1300	0	0
T2	9706	9589	0	0
T3	3010	2622	0	0
T4	10080	9999	0	0
T5	595483	585629	0	0
T6	2390	2246	0	0
T7	1818	1469	0	0
T8	1437	1040	0	0
T9	3061	2559	0	0
T10	52562	51822	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25526875	86561	0	0
T1	1450	51	0	0
T2	9706	0	0	0
T3	3010	0	0	0
T4	10080	0	0	0
T5	595483	0	0	0
T6	2390	0	0	0
T7	1818	0	0	0
T8	1437	0	0	0
T9	3061	0	0	0
T10	52562	579	0	0
T21	0	2175	0	0
T37	0	1876	0	0
T44	0	60	0	0
T72	0	2340	0	0
T93	0	393	0	0
T168	0	52	0	0
T169	0	659	0	0
T170	0	305	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25526875	4586	0	0
T1	1450	3	0	0
T2	9706	0	0	0
T3	3010	0	0	0
T4	10080	0	0	0
T5	595483	91	0	0
T6	2390	1	0	0
T7	1818	5	0	0
T8	1437	0	0	0
T9	3061	5	0	0
T10	52562	0	0	0
T11	0	1	0	0
T13	0	20	0	0
T22	0	3	0	0
T35	0	5	0	0
T40	0	2	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25526875	140	0	0
T18	8652	20	0	0
T19	0	40	0	0
T20	0	40	0	0
T23	0	20	0	0
T24	0	20	0	0
T25	15629	0	0	0
T26	2261	0	0	0
T27	16522	0	0	0
T28	4550	0	0	0
T29	1415	0	0	0
T30	1345	0	0	0
T31	7088	0	0	0
T32	22882	0	0	0
T33	26658	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25526875	4586	0	0
T1	1450	3	0	0
T2	9706	0	0	0
T3	3010	0	0	0
T4	10080	0	0	0
T5	595483	91	0	0
T6	2390	1	0	0
T7	1818	5	0	0
T8	1437	0	0	0
T9	3061	5	0	0
T10	52562	0	0	0
T11	0	1	0	0
T13	0	20	0	0
T22	0	3	0	0
T35	0	5	0	0
T40	0	2	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25526875	1029823	0	0
T1	1450	39	0	0
T2	9706	729	0	0
T3	3010	0	0	0
T4	10080	0	0	0
T5	595483	24665	0	0
T6	2390	0	0	0
T7	1818	0	0	0
T8	1437	0	0	0
T9	3061	0	0	0
T10	52562	5541	0	0
T13	0	1304	0	0
T15	0	23	0	0
T16	0	11	0	0
T22	0	73	0	0
T34	0	490	0	0
T35	0	602	0	0