Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31662

1

T2

21

T3

6

T6

4

auto[1]

30964

1

T2

19

T6

12

T7

66

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32070

1

T2

25

T3

2

T6

6

auto[1]

30556

1

T2

15

T3

4

T6

10

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30647

1

T2

15

T3

3

T6

8

auto[1]

31979

1

T2

25

T3

3

T6

8

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35063

1

T2

23

T3

4

T6

8

auto[1]

27563

1

T2

17

T3

2

T6

8

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30401

1

T2

19

T3

1

T6

14

auto[1]

32225

1

T2

21

T3

5

T6

2

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31810

1

T2

25

T3

4

T6

10

auto[1]

30816

1

T2

15

T3

2

T6

6

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1053

1

T23

3

T13

15

T37

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

822

1

T23

3

T13

12

T37

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1042

1

T2

1

T7

2

T8

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

820

1

T2

1

T7

2

T8

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1029

1

T2

1

T3

1

T7

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

803

1

T2

1

T3

1

T7

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1769

1

T7

1

T8

2

T23

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1534

1

T7

1

T8

2

T23

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1080

1

T7

1

T8

1

T23

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

847

1

T7

1

T8

1

T23

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1051

1

T2

1

T7

2

T8

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

818

1

T7

2

T8

1

T23

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1087

1

T2

2

T7

1

T8

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

855

1

T2

2

T7

1

T8

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1102

1

T2

2

T8

1

T13

10

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

860

1

T2

2

T8

1

T13

7

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1048

1

T7

1

T8

2

T23

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

814

1

T7

1

T8

2

T23

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1056

1

T2

3

T6

1

T7

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

818

1

T6

1

T7

2

T8

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1081

1

T2

1

T7

4

T8

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

839

1

T7

4

T8

1

T23

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1086

1

T2

1

T3

1

T8

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

841

1

T2

1

T3

1

T8

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1072

1

T2

1

T7

4

T8

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

830

1

T2

1

T7

4

T8

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1060

1

T3

1

T7

4

T8

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

818

1

T7

4

T8

2

T13

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1023

1

T3

1

T7

2

T8

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

796

1

T7

2

T8

1

T23

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1079

1

T6

1

T7

1

T8

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

829

1

T6

1

T7

1

T8

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1059

1

T2

1

T6

3

T7

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

839

1

T2

1

T6

3

T7

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1041

1

T2

3

T7

1

T8

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

826

1

T2

3

T7

1

T8

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1134

1

T7

1

T23

1

T13

7

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

858

1

T7

1

T23

1

T13

7

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1063

1

T2

1

T7

4

T23

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

833

1

T2

1

T7

4

T23

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1119

1

T7

1

T8

2

T23

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

875

1

T7

1

T8

2

T23

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1104

1

T8

1

T23

4

T13

17

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

871

1

T8

1

T23

4

T13

12

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1056

1

T7

4

T8

1

T23

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

837

1

T7

4

T8

1

T23

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1113

1

T2

1

T8

3

T23

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

870

1

T2

1

T8

3

T23

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1060

1

T8

3

T13

11

T14

19

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

862

1

T8

3

T13

9

T14

16

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1044

1

T2

2

T6

1

T7

5

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

805

1

T2

1

T6

1

T7

5

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1091

1

T2

1

T7

4

T8

5

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

877

1

T2

1

T7

4

T8

5

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1092

1

T7

1

T8

2

T23

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

871

1

T7

1

T8

2

T23

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1084

1

T6

1

T7

2

T8

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

839

1

T6

1

T7

2

T8

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1085

1

T6

1

T7

2

T23

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

839

1

T6

1

T7

2

T23

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1115

1

T2

1

T7

1

T23

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

863

1

T2

1

T7

1

T23

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1085

1

T7

5

T8

1

T23

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

854

1

T7

5

T8

1

T23

1