Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	485923	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

189621

1

T1

194

T2

14

T3

50

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	354872	1			T1	430		T2	36		T3	76
values[0x0]	160265	1			T1	207		T2	8		T3	64
values[0x1]	160407	1			T1	245		T2	14		T3	56

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	385225	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

290319

1

T1

326

T2

20

T3

75

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2581	1			T1	7		T14	47		T34	4
valid_sources[0x01]	2358	1			T1	2		T2	2		T3	5
valid_sources[0x02]	1994	1			T10	13		T14	54		T33	1
valid_sources[0x03]	2242	1			T1	2		T3	2		T9	1
valid_sources[0x04]	1955	1			T1	1		T3	3		T9	2
valid_sources[0x05]	1798	1			T1	5		T9	1		T14	59
valid_sources[0x06]	2287	1			T9	2		T14	62		T47	1
valid_sources[0x07]	1946	1			T1	9		T10	1		T14	50
valid_sources[0x08]	2137	1			T3	2		T14	47		T34	2
valid_sources[0x09]	1877	1			T1	2		T3	1		T14	42
valid_sources[0x0a]	2993	1			T1	3		T3	2		T14	57
valid_sources[0x0b]	2500	1			T1	1		T9	1		T10	1
valid_sources[0x0c]	1956	1			T1	1		T14	48		T47	6
valid_sources[0x0d]	2005	1			T1	2		T5	2		T9	2
valid_sources[0x0e]	2573	1			T1	4		T14	64		T34	1
valid_sources[0x0f]	2019	1			T3	3		T13	5		T14	61
valid_sources[0x10]	2119	1			T1	2		T3	2		T6	1
valid_sources[0x11]	2781	1			T1	6		T3	3		T9	2
valid_sources[0x12]	2049	1			T1	1		T2	1		T14	61
valid_sources[0x13]	2617	1			T3	2		T10	16		T14	60
valid_sources[0x14]	2354	1			T1	2		T6	2		T14	40
valid_sources[0x15]	2048	1			T1	9		T2	1		T9	1
valid_sources[0x16]	12890	1			T1	2		T14	52		T34	4
valid_sources[0x17]	2251	1			T1	9		T3	1		T9	2
valid_sources[0x18]	2075	1			T1	2		T3	1		T14	61
valid_sources[0x19]	2317	1			T1	6		T9	2		T14	60
valid_sources[0x1a]	1904	1			T1	4		T2	1		T3	5
valid_sources[0x1b]	3897	1			T1	1		T9	1		T14	43
valid_sources[0x1c]	2852	1			T1	11		T14	56		T52	1
valid_sources[0x1d]	2143	1			T1	5		T2	1		T9	1
valid_sources[0x1e]	2019	1			T1	6		T9	1		T14	44
valid_sources[0x1f]	4469	1			T1	3		T2	2		T9	1
valid_sources[0x20]	2667	1			T1	4		T2	2		T10	2
valid_sources[0x21]	2262	1			T3	1		T14	49		T34	6
valid_sources[0x22]	2034	1			T1	2		T9	2		T14	55
valid_sources[0x23]	2827	1			T1	1		T10	27		T14	54
valid_sources[0x24]	3325	1			T1	9		T2	1		T9	1
valid_sources[0x25]	1936	1			T1	3		T3	1		T9	1
valid_sources[0x26]	2282	1			T1	4		T9	1		T10	8
valid_sources[0x27]	3118	1			T1	3		T3	1		T9	1
valid_sources[0x28]	2309	1			T1	8		T9	2		T10	25
valid_sources[0x29]	3809	1			T1	7		T3	2		T13	7
valid_sources[0x2a]	2026	1			T1	1		T9	1		T10	2
valid_sources[0x2b]	3203	1			T2	1		T3	1		T14	56
valid_sources[0x2c]	4118	1			T1	4		T9	1		T10	16
valid_sources[0x2d]	2810	1			T1	4		T10	27		T14	48
valid_sources[0x2e]	1873	1			T1	1		T2	1		T14	47
valid_sources[0x2f]	2112	1			T1	7		T3	1		T14	66
valid_sources[0x30]	2351	1			T1	2		T10	5		T14	64
valid_sources[0x31]	1951	1			T1	1		T14	41		T34	4
valid_sources[0x32]	2421	1			T1	6		T9	2		T10	9
valid_sources[0x33]	2105	1			T1	5		T9	1		T10	23
valid_sources[0x34]	3176	1			T1	4		T2	1		T14	55
valid_sources[0x35]	7166	1			T1	7		T10	35		T14	56
valid_sources[0x36]	1979	1			T1	9		T2	3		T3	1
valid_sources[0x37]	2161	1			T1	5		T14	66		T52	1
valid_sources[0x38]	2264	1			T1	8		T10	19		T14	43
valid_sources[0x39]	2223	1			T1	3		T3	4		T14	49
valid_sources[0x3a]	2059	1			T1	1		T6	3		T14	41
valid_sources[0x3b]	2014	1			T1	1		T14	55		T47	3
valid_sources[0x3c]	2061	1			T2	1		T9	2		T14	56
valid_sources[0x3d]	2178	1			T1	1		T3	3		T14	51
valid_sources[0x3e]	3220	1			T1	2		T9	1		T14	47
valid_sources[0x3f]	2989	1			T1	1		T9	1		T10	12
valid_sources[0x40]	3700	1			T1	13		T9	1		T10	10
valid_sources[0x41]	1978	1			T1	9		T2	1		T9	1
valid_sources[0x42]	2930	1			T1	4		T10	5		T14	63
valid_sources[0x43]	2095	1			T1	3		T3	2		T9	2
valid_sources[0x44]	2131	1			T1	1		T10	3		T14	50
valid_sources[0x45]	2075	1			T1	1		T2	2		T9	1
valid_sources[0x46]	2123	1			T1	10		T2	1		T14	61
valid_sources[0x47]	3338	1			T1	3		T9	1		T10	15
valid_sources[0x48]	2132	1			T1	3		T14	45		T34	2
valid_sources[0x49]	1899	1			T1	1		T3	2		T10	4
valid_sources[0x4a]	2157	1			T1	2		T3	1		T9	1
valid_sources[0x4b]	2376	1			T1	7		T14	53		T33	1
valid_sources[0x4c]	2044	1			T3	3		T14	68		T34	5
valid_sources[0x4d]	2231	1			T1	2		T2	1		T3	3
valid_sources[0x4e]	2705	1			T1	5		T6	1		T10	3
valid_sources[0x4f]	2195	1			T1	4		T9	1		T14	54
valid_sources[0x50]	2011	1			T3	1		T9	1		T10	1
valid_sources[0x51]	3421	1			T1	3		T9	2		T10	39
valid_sources[0x52]	2338	1			T1	6		T10	13		T14	44
valid_sources[0x53]	2336	1			T1	14		T9	2		T14	40
valid_sources[0x54]	2054	1			T1	3		T6	1		T9	1
valid_sources[0x55]	2122	1			T1	4		T9	1		T14	36
valid_sources[0x56]	2032	1			T1	2		T9	1		T10	1
valid_sources[0x57]	2407	1			T1	4		T14	44		T34	3
valid_sources[0x58]	2024	1			T1	4		T2	1		T3	4
valid_sources[0x59]	2363	1			T1	1		T5	1		T6	1
valid_sources[0x5a]	2201	1			T1	3		T9	2		T14	43
valid_sources[0x5b]	2112	1			T1	3		T14	43		T34	3
valid_sources[0x5c]	6612	1			T1	7		T9	1		T10	14
valid_sources[0x5d]	2109	1			T1	3		T9	2		T14	52
valid_sources[0x5e]	3008	1			T1	3		T3	1		T14	38
valid_sources[0x5f]	2912	1			T1	3		T2	1		T3	1
valid_sources[0x60]	2004	1			T1	2		T3	4		T6	3
valid_sources[0x61]	2327	1			T1	3		T2	1		T14	49
valid_sources[0x62]	2118	1			T3	4		T14	42		T35	1
valid_sources[0x63]	2254	1			T1	3		T3	3		T9	4
valid_sources[0x64]	2750	1			T1	3		T9	1		T14	60
valid_sources[0x65]	4219	1			T1	2		T3	1		T9	2
valid_sources[0x66]	2164	1			T1	1		T9	1		T14	56
valid_sources[0x67]	7658	1			T1	6		T9	1		T14	52
valid_sources[0x68]	2271	1			T1	1		T14	53		T34	1
valid_sources[0x69]	2508	1			T1	5		T9	1		T14	52
valid_sources[0x6a]	3150	1			T3	2		T14	46		T47	2
valid_sources[0x6b]	3312	1			T1	6		T14	57		T34	11
valid_sources[0x6c]	2388	1			T1	3		T2	1		T9	1
valid_sources[0x6d]	2161	1			T1	4		T2	1		T3	7
valid_sources[0x6e]	2308	1			T1	6		T3	1		T14	50
valid_sources[0x6f]	2077	1			T1	9		T3	1		T14	61
valid_sources[0x70]	2045	1			T1	4		T3	5		T14	55
valid_sources[0x71]	2132	1			T14	49		T34	6		T27	1
valid_sources[0x72]	2183	1			T1	5		T2	2		T14	54
valid_sources[0x73]	1776	1			T1	6		T3	1		T14	64
valid_sources[0x74]	3275	1			T1	4		T3	2		T14	48
valid_sources[0x75]	2019	1			T1	4		T9	1		T14	60
valid_sources[0x76]	4343	1			T1	3		T9	1		T14	36
valid_sources[0x77]	3155	1			T1	3		T2	2		T13	8
valid_sources[0x78]	3519	1			T1	2		T6	3		T14	42
valid_sources[0x79]	2536	1			T1	2		T3	1		T9	3
valid_sources[0x7a]	4133	1			T1	1		T3	1		T9	1
valid_sources[0x7b]	2170	1			T1	4		T2	1		T13	1
valid_sources[0x7c]	3498	1			T1	4		T6	1		T9	4
valid_sources[0x7d]	2444	1			T1	6		T14	66		T34	5
valid_sources[0x7e]	3133	1			T1	1		T9	1		T14	34
valid_sources[0x7f]	3826	1			T1	1		T7	858		T10	10
valid_sources[0x80]	2372	1			T1	9		T3	1		T9	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

96459

1

T1

81

T2

6

T3

19

values[0x0]

all_enables

biggest_size

60122

1

T1

59

T2

5

T3

19

values[0x1]

all_enables

biggest_size

33040

1

T1

54

T2

3

T3

12