SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35009 | 1 | T1 | 395 | T7 | 413 | T10 | 392 | ||||
others[1] | 34853 | 1 | T1 | 405 | T7 | 389 | T10 | 417 | ||||
others[2] | 35112 | 1 | T1 | 399 | T7 | 410 | T10 | 406 | ||||
others[3] | 58243 | 1 | T1 | 658 | T2 | 2 | T7 | 650 | ||||
false | 17926 | 1 | T1 | 50 | T2 | 2 | T7 | 50 | ||||
true | 27755 | 1 | T1 | 101 | T2 | 5 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34867 | 1 | T1 | 401 | T7 | 381 | T10 | 415 | ||||
others[1] | 34688 | 1 | T1 | 407 | T7 | 434 | T10 | 394 | ||||
others[2] | 35264 | 1 | T1 | 367 | T2 | 1 | T7 | 406 | ||||
others[3] | 58681 | 1 | T1 | 690 | T7 | 655 | T10 | 654 | ||||
false | 11548 | 1 | T1 | 50 | T2 | 4 | T7 | 50 | ||||
true | 21451 | 1 | T1 | 101 | T2 | 7 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 647 | 1 | T14 | 7 | T33 | 1 | T35 | 1 | ||||
others[1] | 680 | 1 | T13 | 2 | T14 | 7 | T29 | 1 | ||||
others[2] | 706 | 1 | T14 | 10 | T35 | 1 | T29 | 1 | ||||
others[3] | 1105 | 1 | T14 | 5 | T29 | 1 | T30 | 1 | ||||
false | 13203 | 1 | T1 | 1 | T2 | 5 | T3 | 1 | ||||
true | 3852 | 1 | T2 | 3 | T13 | 2 | T14 | 63 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |