Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T34,T30

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	22766341	5867	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	22766341	232919	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	22766341	9274768	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	22766341	232867	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	22766341	5867	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	22766341	232919	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	22766341	9274768	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	22766341	232867	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22766341	5867	0	0
T1	29459	19	0	0
T2	6439	0	0	0
T3	2490	0	0	0
T4	15552	0	0	0
T5	831	0	0	0
T6	2345	1	0	0
T7	22931	26	0	0
T8	2257	0	0	0
T9	12134	0	0	0
T10	37861	17	0	0
T14	0	62	0	0
T20	0	22	0	0
T26	0	1	0	0
T30	0	14	0	0
T34	0	23	0	0
T56	0	1	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22766341	232919	0	0
T1	29459	642	0	0
T2	6439	0	0	0
T3	2490	0	0	0
T4	15552	0	0	0
T5	831	0	0	0
T6	2345	15	0	0
T7	22931	574	0	0
T8	2257	0	0	0
T9	12134	0	0	0
T10	37861	647	0	0
T14	0	3696	0	0
T20	0	696	0	0
T26	0	9	0	0
T30	0	372	0	0
T34	0	546	0	0
T56	0	11	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22766341	9274768	0	0
T1	29459	13811	0	0
T2	6439	0	0	0
T3	2490	997	0	0
T4	15552	0	0	0
T5	831	566	0	0
T6	2345	1514	0	0
T7	22931	11802	0	0
T8	2257	0	0	0
T9	12134	5249	0	0
T10	37861	15706	0	0
T14	0	220790	0	0
T47	0	6511	0	0
T52	0	1268	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22766341	232867	0	0
T1	29459	642	0	0
T2	6439	0	0	0
T3	2490	0	0	0
T4	15552	0	0	0
T5	831	0	0	0
T6	2345	15	0	0
T7	22931	574	0	0
T8	2257	0	0	0
T9	12134	0	0	0
T10	37861	647	0	0
T14	0	3696	0	0
T20	0	700	0	0
T26	0	9	0	0
T30	0	372	0	0
T34	0	544	0	0
T56	0	11	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22766341	5867	0	0
T1	29459	19	0	0
T2	6439	0	0	0
T3	2490	0	0	0
T4	15552	0	0	0
T5	831	0	0	0
T6	2345	1	0	0
T7	22931	26	0	0
T8	2257	0	0	0
T9	12134	0	0	0
T10	37861	17	0	0
T14	0	62	0	0
T20	0	22	0	0
T26	0	1	0	0
T30	0	14	0	0
T34	0	23	0	0
T56	0	1	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22766341	232919	0	0
T1	29459	642	0	0
T2	6439	0	0	0
T3	2490	0	0	0
T4	15552	0	0	0
T5	831	0	0	0
T6	2345	15	0	0
T7	22931	574	0	0
T8	2257	0	0	0
T9	12134	0	0	0
T10	37861	647	0	0
T14	0	3696	0	0
T20	0	696	0	0
T26	0	9	0	0
T30	0	372	0	0
T34	0	546	0	0
T56	0	11	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22766341	9274768	0	0
T1	29459	13811	0	0
T2	6439	0	0	0
T3	2490	997	0	0
T4	15552	0	0	0
T5	831	566	0	0
T6	2345	1514	0	0
T7	22931	11802	0	0
T8	2257	0	0	0
T9	12134	5249	0	0
T10	37861	15706	0	0
T14	0	220790	0	0
T47	0	6511	0	0
T52	0	1268	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22766341	232867	0	0
T1	29459	642	0	0
T2	6439	0	0	0
T3	2490	0	0	0
T4	15552	0	0	0
T5	831	0	0	0
T6	2345	15	0	0
T7	22931	574	0	0
T8	2257	0	0	0
T9	12134	0	0	0
T10	37861	647	0	0
T14	0	3696	0	0
T20	0	700	0	0
T26	0	9	0	0
T30	0	372	0	0
T34	0	544	0	0
T56	0	11	0	0