Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	23336002	18526	0	0
intr_enable_rd_A	23336002	35165	0	0
reset_en_rd_A	23336002	1105	0	0
reset_en_regwen_rd_A	23336002	1025	0	0
wake_info_capture_dis_rd_A	23336002	1019	0	0
wakeup_en_rd_A	23336002	1584	0	0
wakeup_en_regwen_rd_A	23336002	1005	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23336002	18526	0	0
T14	505398	90	0	0
T17	44422	0	0	0
T20	0	2	0	0
T21	0	23	0	0
T25	2150	0	0	0
T26	1368	0	0	0
T27	13672	0	0	0
T33	1609	0	0	0
T34	18350	0	0	0
T35	2354	0	0	0
T41	0	80	0	0
T47	15507	0	0	0
T52	1558	0	0	0
T63	0	78	0	0
T129	0	5	0	0
T130	0	37	0	0
T131	0	7	0	0
T132	0	36	0	0
T133	0	10	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23336002	35165	0	0
T2	6439	15	0	0
T3	2490	0	0	0
T4	15552	0	0	0
T5	831	0	0	0
T6	2345	0	0	0
T7	22931	0	0	0
T8	2257	0	0	0
T9	12134	33	0	0
T10	37861	195	0	0
T13	1938	0	0	0
T28	0	32	0	0
T29	0	13	0	0
T47	0	53	0	0
T94	0	12	0	0
T134	0	6	0	0
T135	0	193	0	0
T136	0	65	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23336002	1105	0	0
T55	0	444	0	0
T73	0	2	0	0
T116	0	10	0	0
T118	0	12	0	0
T137	224330	12	0	0
T138	0	5	0	0
T139	0	2	0	0
T140	0	2	0	0
T141	0	2	0	0
T142	0	58	0	0
T143	16389	0	0	0
T144	1022	0	0	0
T145	15510	0	0	0
T146	5045	0	0	0
T147	7690	0	0	0
T148	2692	0	0	0
T149	1224	0	0	0
T150	2906	0	0	0
T151	60066	0	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23336002	1025	0	0
T55	0	452	0	0
T73	0	8	0	0
T116	0	11	0	0
T137	0	3	0	0
T138	0	2	0	0
T139	0	7	0	0
T140	0	7	0	0
T152	373973	6	0	0
T153	0	9	0	0
T154	0	2	0	0
T155	4970	0	0	0
T156	2913	0	0	0
T157	18656	0	0	0
T158	19021	0	0	0
T159	1327	0	0	0
T160	7920	0	0	0
T161	26782	0	0	0
T162	2374	0	0	0
T163	12578	0	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23336002	1019	0	0
T55	0	488	0	0
T73	0	5	0	0
T116	0	6	0	0
T137	0	16	0	0
T138	0	5	0	0
T139	0	1	0	0
T140	0	4	0	0
T141	0	12	0	0
T142	0	25	0	0
T153	121026	2	0	0
T164	3080	0	0	0
T165	30633	0	0	0
T166	50802	0	0	0
T167	1505	0	0	0
T168	4897	0	0	0
T169	25526	0	0	0
T170	5489	0	0	0
T171	1603	0	0	0
T172	5765	0	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23336002	1584	0	0
T55	0	457	0	0
T73	0	14	0	0
T116	0	34	0	0
T118	0	15	0	0
T137	0	8	0	0
T138	0	4	0	0
T141	0	5	0	0
T142	0	134	0	0
T153	121026	7	0	0
T154	0	10	0	0
T164	3080	0	0	0
T165	30633	0	0	0
T166	50802	0	0	0
T167	1505	0	0	0
T168	4897	0	0	0
T169	25526	0	0	0
T170	5489	0	0	0
T171	1603	0	0	0
T172	5765	0	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23336002	1005	0	0
T55	0	479	0	0
T73	0	9	0	0
T116	0	10	0	0
T121	0	26	0	0
T137	0	15	0	0
T138	0	1	0	0
T140	0	2	0	0
T141	0	12	0	0
T142	0	31	0	0
T153	121026	5	0	0
T164	3080	0	0	0
T165	30633	0	0	0
T166	50802	0	0	0
T167	1505	0	0	0
T168	4897	0	0	0
T169	25526	0	0	0
T170	5489	0	0	0
T171	1603	0	0	0
T172	5765	0	0	0