Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	68299023	136920	0	0
StatusRise_A	68299023	153330	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68299023	136920	0	0
T1	88377	207	0	0
T2	19317	21	0	0
T3	7470	43	0	0
T4	46656	3	0	0
T5	2493	6	0	0
T6	7035	6	0	0
T7	68793	236	0	0
T8	6771	0	0	0
T9	36402	27	0	0
T10	113583	205	0	0
T13	0	15	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68299023	153330	0	0
T1	88377	209	0	0
T2	19317	27	0	0
T3	7470	46	0	0
T4	46656	6	0	0
T5	2493	9	0	0
T6	7035	9	0	0
T7	68793	242	0	0
T8	6771	9	0	0
T9	36402	29	0	0
T10	113583	208	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	22766341	50862	0	0
StatusRise_A	22766341	56753	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22766341	50862	0	0
T1	29459	80	0	0
T2	6439	7	0	0
T3	2490	15	0	0
T4	15552	1	0	0
T5	831	2	0	0
T6	2345	2	0	0
T7	22931	89	0	0
T8	2257	0	0	0
T9	12134	12	0	0
T10	37861	83	0	0
T13	0	5	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22766341	56753	0	0
T1	29459	81	0	0
T2	6439	9	0	0
T3	2490	16	0	0
T4	15552	2	0	0
T5	831	3	0	0
T6	2345	3	0	0
T7	22931	91	0	0
T8	2257	3	0	0
T9	12134	13	0	0
T10	37861	84	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	22766341	50862	0	0
StatusRise_A	22766341	56753	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22766341	50862	0	0
T1	29459	80	0	0
T2	6439	7	0	0
T3	2490	15	0	0
T4	15552	1	0	0
T5	831	2	0	0
T6	2345	2	0	0
T7	22931	89	0	0
T8	2257	0	0	0
T9	12134	12	0	0
T10	37861	83	0	0
T13	0	5	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22766341	56753	0	0
T1	29459	81	0	0
T2	6439	9	0	0
T3	2490	16	0	0
T4	15552	2	0	0
T5	831	3	0	0
T6	2345	3	0	0
T7	22931	91	0	0
T8	2257	3	0	0
T9	12134	13	0	0
T10	37861	84	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	22766341	35196	0	0
StatusRise_A	22766341	39824	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22766341	35196	0	0
T1	29459	47	0	0
T2	6439	7	0	0
T3	2490	13	0	0
T4	15552	1	0	0
T5	831	2	0	0
T6	2345	2	0	0
T7	22931	58	0	0
T8	2257	0	0	0
T9	12134	3	0	0
T10	37861	39	0	0
T13	0	5	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22766341	39824	0	0
T1	29459	47	0	0
T2	6439	9	0	0
T3	2490	14	0	0
T4	15552	2	0	0
T5	831	3	0	0
T6	2345	3	0	0
T7	22931	60	0	0
T8	2257	3	0	0
T9	12134	3	0	0
T10	37861	40	0	0