Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	22766951	5630	0	0
EscTimeoutStoppedByClReset_A	22766341	3164154	0	0
EscTimeoutTriggersReset_A	4864955	310	0	0
RomAllowActiveState_A	22766341	56374	0	0
RomAllowCheckGoodState_A	22766341	56424	0	0
RomBlockActiveState_A	22766341	26067	0	0
RomBlockCheckGoodState_A	22766341	393957	0	0
RomIntgChkDisFalse_A	22766341	22102519	0	0
RomIntgChkDisTrue_A	22766341	151419	0	0
RstreqChkEsctimeout_A	22766341	4212	0	0
RstreqChkFsmterm_A	22766341	200	0	0
RstreqChkGlbesc_A	22766341	4212	0	0
RstreqChkMainpd_A	22766341	858970	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22766951	5630	0	0
T4	15552	278	0	0
T5	832	0	0	0
T6	2346	0	0	0
T7	22932	0	0	0
T8	2257	0	0	0
T9	12135	0	0	0
T10	37861	0	0	0
T11	0	13	0	0
T12	0	176	0	0
T13	1939	0	0	0
T14	505398	0	0	0
T47	15507	0	0	0
T174	0	163	0	0
T175	0	15	0	0
T176	0	6	0	0
T177	0	11	0	0
T178	0	57	0	0
T179	0	33	0	0
T180	0	23	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22766341	3164154	0	0
T1	29459	5315	0	0
T2	6439	366	0	0
T3	2490	9	0	0
T4	15552	47	0	0
T5	831	10	0	0
T6	2345	40	0	0
T7	22931	3309	0	0
T8	2257	37	0	0
T9	12134	2241	0	0
T10	37861	6977	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4864955	310	0	0
T4	210	3	0	0
T5	603	0	0	0
T6	212	0	0	0
T7	8258	0	0	0
T8	232	0	0	0
T9	1275	0	0	0
T10	7654	0	0	0
T11	0	2	0	0
T12	0	2	0	0
T13	553	0	0	0
T14	50353	0	0	0
T47	1703	0	0	0
T174	0	2	0	0
T175	0	4	0	0
T176	0	5	0	0
T177	0	2	0	0
T178	0	3	0	0
T181	0	3	0	0
T182	0	2	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22766341	56374	0	0
T1	29459	81	0	0
T2	6439	9	0	0
T3	2490	16	0	0
T4	15552	2	0	0
T5	831	3	0	0
T6	2345	3	0	0
T7	22931	91	0	0
T8	2257	3	0	0
T9	12134	13	0	0
T10	37861	84	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22766341	56424	0	0
T1	29459	81	0	0
T2	6439	9	0	0
T3	2490	16	0	0
T4	15552	2	0	0
T5	831	3	0	0
T6	2345	3	0	0
T7	22931	91	0	0
T8	2257	3	0	0
T9	12134	13	0	0
T10	37861	84	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22766341	26067	0	0
T2	6439	1242	0	0
T3	2490	0	0	0
T4	15552	0	0	0
T5	831	0	0	0
T6	2345	0	0	0
T7	22931	0	0	0
T8	2257	0	0	0
T9	12134	0	0	0
T10	37861	0	0	0
T13	1938	311	0	0
T22	0	22	0	0
T34	0	12	0	0
T135	0	14	0	0
T183	0	1406	0	0
T184	0	528	0	0
T185	0	7	0	0
T186	0	7	0	0
T187	0	647	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22766341	393957	0	0
T1	29459	2247	0	0
T2	6439	1020	0	0
T3	2490	0	0	0
T4	15552	0	0	0
T5	831	0	0	0
T6	2345	0	0	0
T7	22931	1351	0	0
T8	2257	0	0	0
T9	12134	0	0	0
T10	37861	2232	0	0
T13	0	102	0	0
T14	0	2365	0	0
T20	0	895	0	0
T22	0	1408	0	0
T30	0	413	0	0
T34	0	1281	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22766341	22102519	0	0
T1	29459	29368	0	0
T2	6439	6135	0	0
T3	2490	2434	0	0
T4	15552	15495	0	0
T5	831	774	0	0
T6	2345	2289	0	0
T7	22931	22779	0	0
T8	2257	2050	0	0
T9	12134	12059	0	0
T10	37861	37810	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22766341	151419	0	0
T2	6439	167	0	0
T3	2490	0	0	0
T4	15552	0	0	0
T5	831	0	0	0
T6	2345	0	0	0
T7	22931	0	0	0
T8	2257	0	0	0
T9	12134	0	0	0
T10	37861	0	0	0
T13	1938	159	0	0
T22	0	465	0	0
T135	0	340	0	0
T183	0	187	0	0
T184	0	1367	0	0
T188	0	2318	0	0
T189	0	1398	0	0
T190	0	63	0	0
T191	0	656	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22766341	4212	0	0
T2	6439	3	0	0
T3	2490	0	0	0
T4	15552	1	0	0
T5	831	0	0	0
T6	2345	0	0	0
T7	22931	0	0	0
T8	2257	0	0	0
T9	12134	0	0	0
T10	37861	0	0	0
T13	1938	2	0	0
T14	0	69	0	0
T17	0	20	0	0
T20	0	49	0	0
T29	0	6	0	0
T30	0	14	0	0
T35	0	2	0	0
T36	0	8	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22766341	200	0	0
T17	44422	40	0	0
T18	0	40	0	0
T19	0	40	0	0
T20	104792	0	0	0
T23	0	40	0	0
T24	0	40	0	0
T25	2150	0	0	0
T26	1368	0	0	0
T27	13672	0	0	0
T28	5785	0	0	0
T29	4703	0	0	0
T30	33208	0	0	0
T31	3588	0	0	0
T32	10999	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22766341	4212	0	0
T2	6439	3	0	0
T3	2490	0	0	0
T4	15552	1	0	0
T5	831	0	0	0
T6	2345	0	0	0
T7	22931	0	0	0
T8	2257	0	0	0
T9	12134	0	0	0
T10	37861	0	0	0
T13	1938	2	0	0
T14	0	69	0	0
T17	0	20	0	0
T20	0	49	0	0
T29	0	6	0	0
T30	0	14	0	0
T35	0	2	0	0
T36	0	8	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22766341	858970	0	0
T1	29459	2203	0	0
T2	6439	1129	0	0
T3	2490	0	0	0
T4	15552	0	0	0
T5	831	0	0	0
T6	2345	0	0	0
T7	22931	1784	0	0
T8	2257	6	0	0
T9	12134	0	0	0
T10	37861	2669	0	0
T13	0	52	0	0
T14	0	14154	0	0
T33	0	153	0	0
T34	0	1595	0	0
T35	0	66	0	0