Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	350980	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

140961

1

T1

214

T2

51

T3

39

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	259177	1			T1	417		T2	103		T3	85
values[0x0]	116583	1			T1	229		T2	58		T3	48
values[0x1]	116181	1			T1	223		T2	52		T3	58

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	277741	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

214200

1

T1

353

T2

91

T3

66

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1568	1			T5	4		T7	10		T8	3
valid_sources[0x01]	1516	1			T5	3		T8	3		T22	1
valid_sources[0x02]	1264	1			T5	2		T8	5		T14	21
valid_sources[0x03]	1541	1			T2	1		T5	1		T8	1
valid_sources[0x04]	1554	1			T5	5		T8	2		T22	2
valid_sources[0x05]	2584	1			T2	1		T5	2		T7	3
valid_sources[0x06]	3025	1			T5	5		T8	4		T14	28
valid_sources[0x07]	2417	1			T2	1		T5	1		T8	5
valid_sources[0x08]	2469	1			T5	5		T8	6		T22	2
valid_sources[0x09]	1981	1			T5	4		T8	4		T13	1
valid_sources[0x0a]	1933	1			T2	2		T5	9		T7	7
valid_sources[0x0b]	1779	1			T2	2		T5	4		T7	6
valid_sources[0x0c]	1341	1			T2	1		T5	6		T7	3
valid_sources[0x0d]	2147	1			T2	1		T5	2		T8	2
valid_sources[0x0e]	1598	1			T2	1		T5	4		T7	3
valid_sources[0x0f]	1747	1			T2	1		T5	3		T8	5
valid_sources[0x10]	1596	1			T2	3		T5	3		T14	26
valid_sources[0x11]	1520	1			T2	2		T5	6		T7	2
valid_sources[0x12]	1506	1			T5	6		T8	1		T22	4
valid_sources[0x13]	1626	1			T2	1		T5	3		T8	2
valid_sources[0x14]	1632	1			T5	1		T7	4		T8	3
valid_sources[0x15]	2523	1			T2	2		T5	3		T8	5
valid_sources[0x16]	1856	1			T2	1		T5	2		T7	1
valid_sources[0x17]	1693	1			T2	1		T5	3		T8	4
valid_sources[0x18]	1610	1			T2	2		T5	1		T7	1
valid_sources[0x19]	4443	1			T5	3		T8	5		T14	27
valid_sources[0x1a]	1670	1			T2	1		T5	5		T8	4
valid_sources[0x1b]	2344	1			T2	2		T5	7		T7	2
valid_sources[0x1c]	1468	1			T5	2		T7	2		T8	3
valid_sources[0x1d]	1498	1			T2	1		T5	6		T8	8
valid_sources[0x1e]	2581	1			T5	3		T8	5		T22	6
valid_sources[0x1f]	2437	1			T2	1		T5	1		T8	4
valid_sources[0x20]	1417	1			T5	6		T7	5		T8	3
valid_sources[0x21]	1832	1			T5	5		T8	3		T78	2
valid_sources[0x22]	1576	1			T2	2		T5	2		T7	3
valid_sources[0x23]	1658	1			T5	3		T8	4		T14	23
valid_sources[0x24]	1510	1			T2	1		T5	5		T8	3
valid_sources[0x25]	2411	1			T5	3		T8	6		T22	2
valid_sources[0x26]	1515	1			T5	9		T8	6		T22	6
valid_sources[0x27]	2473	1			T2	2		T5	4		T8	3
valid_sources[0x28]	1607	1			T5	3		T8	2		T14	28
valid_sources[0x29]	2675	1			T5	2		T10	49		T22	3
valid_sources[0x2a]	2305	1			T2	1		T5	4		T8	8
valid_sources[0x2b]	2440	1			T2	1		T5	6		T8	6
valid_sources[0x2c]	1656	1			T2	1		T5	3		T8	6
valid_sources[0x2d]	2393	1			T2	1		T5	1		T8	2
valid_sources[0x2e]	3564	1			T2	5		T5	4		T8	2
valid_sources[0x2f]	2599	1			T5	3		T8	4		T22	2
valid_sources[0x30]	1658	1			T2	1		T5	4		T8	4
valid_sources[0x31]	1468	1			T2	1		T5	2		T8	5
valid_sources[0x32]	1859	1			T5	1		T8	3		T22	1
valid_sources[0x33]	3877	1			T5	3		T8	5		T23	1625
valid_sources[0x34]	1431	1			T2	3		T5	2		T8	2
valid_sources[0x35]	1607	1			T2	1		T5	2		T8	4
valid_sources[0x36]	2239	1			T2	2		T8	4		T22	11
valid_sources[0x37]	1774	1			T5	1		T7	2		T8	6
valid_sources[0x38]	1366	1			T2	2		T5	7		T8	2
valid_sources[0x39]	1543	1			T5	2		T8	2		T22	7
valid_sources[0x3a]	1587	1			T5	5		T8	4		T22	1
valid_sources[0x3b]	1478	1			T5	6		T8	2		T22	5
valid_sources[0x3c]	1462	1			T2	2		T4	1		T5	5
valid_sources[0x3d]	1511	1			T2	2		T5	3		T8	4
valid_sources[0x3e]	2404	1			T5	1		T8	2		T22	3
valid_sources[0x3f]	1433	1			T2	2		T5	3		T8	10
valid_sources[0x40]	1793	1			T5	5		T8	4		T22	2
valid_sources[0x41]	1456	1			T5	5		T8	5		T22	5
valid_sources[0x42]	1934	1			T2	2		T5	5		T8	4
valid_sources[0x43]	1510	1			T5	3		T8	4		T22	4
valid_sources[0x44]	1320	1			T5	5		T8	7		T13	1
valid_sources[0x45]	2597	1			T5	3		T8	6		T22	13
valid_sources[0x46]	2977	1			T5	8		T8	4		T22	3
valid_sources[0x47]	1308	1			T5	1		T7	3		T8	2
valid_sources[0x48]	2190	1			T2	2		T5	5		T8	2
valid_sources[0x49]	1521	1			T2	1		T5	6		T8	2
valid_sources[0x4a]	2654	1			T2	2		T5	3		T7	1
valid_sources[0x4b]	1780	1			T5	2		T8	1		T22	8
valid_sources[0x4c]	3404	1			T2	1		T5	6		T7	4
valid_sources[0x4d]	2367	1			T2	1		T5	2		T8	5
valid_sources[0x4e]	2580	1			T2	3		T5	2		T8	2
valid_sources[0x4f]	1847	1			T2	2		T5	4		T8	5
valid_sources[0x50]	1661	1			T2	3		T5	4		T8	3
valid_sources[0x51]	1441	1			T5	3		T8	3		T22	1
valid_sources[0x52]	1984	1			T2	1		T5	4		T7	8
valid_sources[0x53]	2561	1			T1	869		T5	1		T7	2
valid_sources[0x54]	1637	1			T5	3		T8	1		T13	2
valid_sources[0x55]	1314	1			T5	4		T8	5		T14	19
valid_sources[0x56]	1790	1			T5	3		T8	5		T22	4
valid_sources[0x57]	1434	1			T2	3		T5	1		T8	3
valid_sources[0x58]	1573	1			T2	1		T5	6		T8	2
valid_sources[0x59]	1557	1			T2	2		T5	5		T13	3
valid_sources[0x5a]	2020	1			T5	5		T6	121		T8	6
valid_sources[0x5b]	1712	1			T5	6		T8	2		T22	8
valid_sources[0x5c]	1640	1			T2	1		T5	2		T8	3
valid_sources[0x5d]	1409	1			T5	2		T7	7		T8	5
valid_sources[0x5e]	1437	1			T5	2		T7	1		T8	2
valid_sources[0x5f]	1671	1			T2	1		T5	4		T8	3
valid_sources[0x60]	1382	1			T5	2		T8	5		T22	7
valid_sources[0x61]	1401	1			T5	4		T22	3		T51	10
valid_sources[0x62]	1687	1			T5	1		T7	1		T8	6
valid_sources[0x63]	1523	1			T5	1		T8	1		T13	1
valid_sources[0x64]	2586	1			T2	2		T5	2		T7	1
valid_sources[0x65]	1464	1			T5	3		T8	7		T22	1
valid_sources[0x66]	2638	1			T5	4		T8	1		T51	32
valid_sources[0x67]	1396	1			T2	2		T5	3		T8	6
valid_sources[0x68]	1730	1			T2	1		T5	2		T8	5
valid_sources[0x69]	1650	1			T5	5		T8	1		T13	1
valid_sources[0x6a]	5521	1			T5	3		T8	3		T22	11
valid_sources[0x6b]	2495	1			T5	2		T7	3		T8	10
valid_sources[0x6c]	1338	1			T2	1		T5	3		T22	1
valid_sources[0x6d]	3062	1			T2	1		T5	1		T8	4
valid_sources[0x6e]	1383	1			T2	1		T5	6		T8	3
valid_sources[0x6f]	1565	1			T5	3		T8	5		T22	6
valid_sources[0x70]	1471	1			T5	5		T8	4		T13	1
valid_sources[0x71]	1801	1			T2	1		T5	1		T8	4
valid_sources[0x72]	2465	1			T2	1		T5	7		T7	3
valid_sources[0x73]	3735	1			T2	1		T5	5		T8	4
valid_sources[0x74]	1405	1			T2	2		T5	6		T8	2
valid_sources[0x75]	1723	1			T2	1		T5	1		T8	3
valid_sources[0x76]	1563	1			T5	2		T7	3		T8	2
valid_sources[0x77]	1323	1			T2	1		T5	4		T7	4
valid_sources[0x78]	1651	1			T5	5		T8	7		T22	7
valid_sources[0x79]	3067	1			T2	2		T5	2		T14	25
valid_sources[0x7a]	1678	1			T2	1		T5	5		T8	2
valid_sources[0x7b]	2187	1			T5	2		T8	2		T22	1
valid_sources[0x7c]	1491	1			T5	3		T8	4		T14	26
valid_sources[0x7d]	1353	1			T2	1		T5	5		T8	1
valid_sources[0x7e]	1550	1			T5	3		T7	2		T8	2
valid_sources[0x7f]	1696	1			T5	2		T8	5		T22	1
valid_sources[0x80]	2072	1			T2	2		T5	3		T8	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

71585

1

T1

90

T2

20

T3

13

values[0x0]

all_enables

biggest_size

44729

1

T1

77

T2

23

T3

14

values[0x1]

all_enables

biggest_size

24647

1

T1

47

T2

8

T3

12