SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35080 | 1 | T1 | 317 | T5 | 290 | T8 | 408 | ||||
others[1] | 35236 | 1 | T1 | 290 | T5 | 319 | T8 | 405 | ||||
others[2] | 34919 | 1 | T1 | 289 | T5 | 307 | T8 | 366 | ||||
others[3] | 58226 | 1 | T1 | 507 | T5 | 493 | T8 | 680 | ||||
false | 13448 | 1 | T1 | 50 | T2 | 24 | T5 | 50 | ||||
true | 21846 | 1 | T1 | 52 | T2 | 26 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34912 | 1 | T1 | 289 | T5 | 307 | T8 | 382 | ||||
others[1] | 35249 | 1 | T1 | 316 | T5 | 282 | T8 | 399 | ||||
others[2] | 34949 | 1 | T1 | 279 | T5 | 304 | T8 | 417 | ||||
others[3] | 58477 | 1 | T1 | 519 | T5 | 516 | T8 | 655 | ||||
false | 9348 | 1 | T1 | 50 | T2 | 12 | T5 | 50 | ||||
true | 17779 | 1 | T1 | 52 | T2 | 14 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 553 | 1 | T6 | 1 | T13 | 1 | T23 | 1 | ||||
others[1] | 490 | 1 | T14 | 4 | T35 | 1 | T137 | 5 | ||||
others[2] | 552 | 1 | T14 | 4 | T137 | 6 | T57 | 9 | ||||
others[3] | 913 | 1 | T6 | 2 | T13 | 2 | T23 | 3 | ||||
false | 9902 | 1 | T1 | 2 | T2 | 2 | T3 | 1 | ||||
true | 2576 | 1 | T6 | 4 | T9 | 5 | T13 | 2 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |