Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T23,T14

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	16205928	4674	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	16205928	192196	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	16205928	6424033	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	16205928	192207	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	16205928	4674	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	16205928	192196	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	16205928	6424033	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	16205928	192207	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16205928	4674	0	0
T1	27306	18	0	0
T2	15959	6	0	0
T3	4211	0	0	0
T4	813	0	0	0
T5	19041	25	0	0
T6	7806	0	0	0
T7	2269	0	0	0
T8	18948	20	0	0
T9	2603	0	0	0
T10	2566	0	0	0
T14	0	78	0	0
T22	0	23	0	0
T23	0	16	0	0
T36	0	1	0	0
T39	0	3	0	0
T76	0	1	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16205928	192196	0	0
T1	27306	808	0	0
T2	15959	453	0	0
T3	4211	0	0	0
T4	813	0	0	0
T5	19041	502	0	0
T6	7806	0	0	0
T7	2269	0	0	0
T8	18948	495	0	0
T9	2603	0	0	0
T10	2566	0	0	0
T14	0	2086	0	0
T22	0	937	0	0
T23	0	1042	0	0
T36	0	11	0	0
T39	0	260	0	0
T76	0	12	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16205928	6424033	0	0
T1	27306	11290	0	0
T2	15959	9149	0	0
T3	4211	1645	0	0
T4	813	0	0	0
T5	19041	10148	0	0
T6	7806	0	0	0
T7	2269	1336	0	0
T8	18948	8597	0	0
T9	2603	0	0	0
T10	2566	1724	0	0
T22	0	19384	0	0
T23	0	36409	0	0
T36	0	781	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16205928	192207	0	0
T1	27306	808	0	0
T2	15959	453	0	0
T3	4211	0	0	0
T4	813	0	0	0
T5	19041	502	0	0
T6	7806	0	0	0
T7	2269	0	0	0
T8	18948	495	0	0
T9	2603	0	0	0
T10	2566	0	0	0
T14	0	2086	0	0
T22	0	937	0	0
T23	0	1042	0	0
T36	0	11	0	0
T39	0	260	0	0
T76	0	12	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16205928	4674	0	0
T1	27306	18	0	0
T2	15959	6	0	0
T3	4211	0	0	0
T4	813	0	0	0
T5	19041	25	0	0
T6	7806	0	0	0
T7	2269	0	0	0
T8	18948	20	0	0
T9	2603	0	0	0
T10	2566	0	0	0
T14	0	78	0	0
T22	0	23	0	0
T23	0	16	0	0
T36	0	1	0	0
T39	0	3	0	0
T76	0	1	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16205928	192196	0	0
T1	27306	808	0	0
T2	15959	453	0	0
T3	4211	0	0	0
T4	813	0	0	0
T5	19041	502	0	0
T6	7806	0	0	0
T7	2269	0	0	0
T8	18948	495	0	0
T9	2603	0	0	0
T10	2566	0	0	0
T14	0	2086	0	0
T22	0	937	0	0
T23	0	1042	0	0
T36	0	11	0	0
T39	0	260	0	0
T76	0	12	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16205928	6424033	0	0
T1	27306	11290	0	0
T2	15959	9149	0	0
T3	4211	1645	0	0
T4	813	0	0	0
T5	19041	10148	0	0
T6	7806	0	0	0
T7	2269	1336	0	0
T8	18948	8597	0	0
T9	2603	0	0	0
T10	2566	1724	0	0
T22	0	19384	0	0
T23	0	36409	0	0
T36	0	781	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16205928	192207	0	0
T1	27306	808	0	0
T2	15959	453	0	0
T3	4211	0	0	0
T4	813	0	0	0
T5	19041	502	0	0
T6	7806	0	0	0
T7	2269	0	0	0
T8	18948	495	0	0
T9	2603	0	0	0
T10	2566	0	0	0
T14	0	2086	0	0
T22	0	937	0	0
T23	0	1042	0	0
T36	0	11	0	0
T39	0	260	0	0
T76	0	12	0	0