Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	16788885	14827	0	0
intr_enable_rd_A	16788885	29059	0	0
reset_en_rd_A	16788885	1278	0	0
reset_en_regwen_rd_A	16788885	1174	0	0
wake_info_capture_dis_rd_A	16788885	1293	0	0
wakeup_en_rd_A	16788885	1805	0	0
wakeup_en_regwen_rd_A	16788885	1258	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16788885	14827	0	0
T12	15055	0	0	0
T14	182239	11	0	0
T15	0	26	0	0
T16	1135	0	0	0
T17	4271	0	0	0
T24	0	5	0	0
T35	4359	0	0	0
T39	1356	0	0	0
T45	0	32	0	0
T46	0	175	0	0
T47	0	13	0	0
T57	4577	0	0	0
T76	17667	0	0	0
T79	0	16	0	0
T80	0	12	0	0
T135	0	35	0	0
T136	0	72	0	0
T137	1930	0	0	0
T138	4674	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16788885	29059	0	0
T2	15959	46	0	0
T3	4211	0	0	0
T4	813	0	0	0
T5	19041	0	0	0
T6	7806	0	0	0
T7	2269	0	0	0
T8	18948	0	0	0
T9	2603	0	0	0
T10	2566	0	0	0
T13	0	20	0	0
T14	0	1681	0	0
T22	42547	0	0	0
T24	0	721	0	0
T30	0	32	0	0
T31	0	24	0	0
T78	0	13	0	0
T131	0	21	0	0
T139	0	70	0	0
T140	0	4	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16788885	1278	0	0
T12	15055	0	0	0
T14	182239	11	0	0
T16	1135	0	0	0
T17	4271	0	0	0
T24	0	5	0	0
T35	4359	0	0	0
T39	1356	0	0	0
T57	4577	0	0	0
T60	0	46	0	0
T76	17667	0	0	0
T80	0	22	0	0
T81	0	2	0	0
T93	0	9	0	0
T137	1930	0	0	0
T138	4674	0	0	0
T141	0	8	0	0
T142	0	1	0	0
T143	0	5	0	0
T144	0	5	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16788885	1174	0	0
T12	15055	0	0	0
T14	182239	18	0	0
T16	1135	0	0	0
T17	4271	0	0	0
T24	0	15	0	0
T35	4359	0	0	0
T39	1356	0	0	0
T57	4577	0	0	0
T60	0	29	0	0
T76	17667	0	0	0
T80	0	6	0	0
T81	0	4	0	0
T93	0	17	0	0
T137	1930	0	0	0
T138	4674	0	0	0
T141	0	17	0	0
T142	0	7	0	0
T143	0	2	0	0
T144	0	9	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16788885	1293	0	0
T12	15055	0	0	0
T14	182239	14	0	0
T16	1135	0	0	0
T17	4271	0	0	0
T24	0	8	0	0
T35	4359	0	0	0
T39	1356	0	0	0
T57	4577	0	0	0
T60	0	19	0	0
T76	17667	0	0	0
T80	0	25	0	0
T81	0	9	0	0
T93	0	21	0	0
T137	1930	0	0	0
T138	4674	0	0	0
T141	0	8	0	0
T142	0	28	0	0
T143	0	15	0	0
T144	0	9	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16788885	1805	0	0
T12	15055	0	0	0
T14	182239	5	0	0
T16	1135	0	0	0
T17	4271	0	0	0
T24	0	14	0	0
T35	4359	0	0	0
T39	1356	0	0	0
T57	4577	0	0	0
T60	0	13	0	0
T76	17667	0	0	0
T80	0	14	0	0
T81	0	11	0	0
T93	0	13	0	0
T137	1930	0	0	0
T138	4674	0	0	0
T141	0	11	0	0
T142	0	6	0	0
T143	0	13	0	0
T144	0	12	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16788885	1258	0	0
T12	15055	0	0	0
T14	182239	20	0	0
T16	1135	0	0	0
T17	4271	0	0	0
T24	0	1	0	0
T35	4359	0	0	0
T39	1356	0	0	0
T57	4577	0	0	0
T60	0	21	0	0
T76	17667	0	0	0
T80	0	14	0	0
T93	0	24	0	0
T137	1930	0	0	0
T138	4674	0	0	0
T141	0	6	0	0
T142	0	5	0	0
T143	0	7	0	0
T144	0	9	0	0
T145	0	7	0	0