Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	48617784	97977	0	0
StatusRise_A	48617784	110316	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48617784	97977	0	0
T1	81918	202	0	0
T2	47877	51	0	0
T3	12633	42	0	0
T4	2439	3	0	0
T5	57123	221	0	0
T6	23418	54	0	0
T7	6807	41	0	0
T8	56844	209	0	0
T9	7809	27	0	0
T10	7698	22	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48617784	110316	0	0
T1	81918	207	0	0
T2	47877	57	0	0
T3	12633	44	0	0
T4	2439	9	0	0
T5	57123	226	0	0
T6	23418	60	0	0
T7	6807	43	0	0
T8	56844	211	0	0
T9	7809	33	0	0
T10	7698	25	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	16205928	36540	0	0
StatusRise_A	16205928	40937	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16205928	36540	0	0
T1	27306	79	0	0
T2	15959	21	0	0
T3	4211	15	0	0
T4	813	1	0	0
T5	19041	91	0	0
T6	7806	18	0	0
T7	2269	14	0	0
T8	18948	88	0	0
T9	2603	9	0	0
T10	2566	8	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16205928	40937	0	0
T1	27306	81	0	0
T2	15959	23	0	0
T3	4211	16	0	0
T4	813	3	0	0
T5	19041	93	0	0
T6	7806	20	0	0
T7	2269	15	0	0
T8	18948	89	0	0
T9	2603	11	0	0
T10	2566	9	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	16205928	36540	0	0
StatusRise_A	16205928	40937	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16205928	36540	0	0
T1	27306	79	0	0
T2	15959	21	0	0
T3	4211	15	0	0
T4	813	1	0	0
T5	19041	91	0	0
T6	7806	18	0	0
T7	2269	14	0	0
T8	18948	88	0	0
T9	2603	9	0	0
T10	2566	8	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16205928	40937	0	0
T1	27306	81	0	0
T2	15959	23	0	0
T3	4211	16	0	0
T4	813	3	0	0
T5	19041	93	0	0
T6	7806	20	0	0
T7	2269	15	0	0
T8	18948	89	0	0
T9	2603	11	0	0
T10	2566	9	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	16205928	24897	0	0
StatusRise_A	16205928	28442	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16205928	24897	0	0
T1	27306	44	0	0
T2	15959	9	0	0
T3	4211	12	0	0
T4	813	1	0	0
T5	19041	39	0	0
T6	7806	18	0	0
T7	2269	13	0	0
T8	18948	33	0	0
T9	2603	9	0	0
T10	2566	6	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16205928	28442	0	0
T1	27306	45	0	0
T2	15959	11	0	0
T3	4211	12	0	0
T4	813	3	0	0
T5	19041	40	0	0
T6	7806	20	0	0
T7	2269	13	0	0
T8	18948	33	0	0
T9	2603	11	0	0
T10	2566	7	0	0