Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	16206496	5548	0	0
EscTimeoutStoppedByClReset_A	16205928	2220844	0	0
EscTimeoutTriggersReset_A	3404105	332	0	0
RomAllowActiveState_A	16205928	40492	0	0
RomAllowCheckGoodState_A	16205928	40543	0	0
RomBlockActiveState_A	16205928	28828	0	0
RomBlockCheckGoodState_A	16205928	350273	0	0
RomIntgChkDisFalse_A	16205928	15671056	0	0
RomIntgChkDisTrue_A	16205928	143405	0	0
RstreqChkEsctimeout_A	16205928	2940	0	0
RstreqChkFsmterm_A	16205928	180	0	0
RstreqChkGlbesc_A	16205928	2940	0	0
RstreqChkMainpd_A	16205928	700558	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16206496	5548	0	0
T4	814	1	0	0
T5	19042	0	0	0
T6	7806	0	0	0
T7	2269	0	0	0
T8	18949	0	0	0
T9	2603	0	0	0
T10	2566	0	0	0
T11	763	0	0	0
T12	0	45	0	0
T22	42548	0	0	0
T29	0	243	0	0
T36	1063	0	0	0
T88	0	59	0	0
T89	0	39	0	0
T90	0	30	0	0
T95	0	21	0	0
T99	0	5	0	0
T146	0	110	0	0
T147	0	84	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16205928	2220844	0	0
T1	27306	6447	0	0
T2	15959	2145	0	0
T3	4211	475	0	0
T4	813	43	0	0
T5	19041	2498	0	0
T6	7806	391	0	0
T7	2269	0	0	0
T8	18948	3605	0	0
T9	2603	222	0	0
T10	2566	166	0	0
T22	0	8210	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3404105	332	0	0
T4	257	4	0	0
T5	9277	0	0	0
T6	775	0	0	0
T7	529	0	0	0
T8	7433	0	0	0
T9	409	0	0	0
T10	2227	0	0	0
T11	284	4	0	0
T12	0	3	0	0
T22	6097	0	0	0
T29	0	3	0	0
T36	359	0	0	0
T88	0	3	0	0
T95	0	2	0	0
T99	0	10	0	0
T146	0	2	0	0
T147	0	3	0	0
T148	0	5	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16205928	40492	0	0
T1	27306	81	0	0
T2	15959	23	0	0
T3	4211	16	0	0
T4	813	3	0	0
T5	19041	93	0	0
T6	7806	13	0	0
T7	2269	15	0	0
T8	18948	89	0	0
T9	2603	11	0	0
T10	2566	9	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16205928	40543	0	0
T1	27306	81	0	0
T2	15959	23	0	0
T3	4211	16	0	0
T4	813	3	0	0
T5	19041	93	0	0
T6	7806	14	0	0
T7	2269	15	0	0
T8	18948	89	0	0
T9	2603	11	0	0
T10	2566	9	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16205928	28828	0	0
T5	19041	21	0	0
T6	7806	0	0	0
T7	2269	0	0	0
T8	18948	4	0	0
T9	2603	0	0	0
T10	2566	0	0	0
T11	763	0	0	0
T13	3090	419	0	0
T22	42547	0	0	0
T27	0	190	0	0
T36	1063	0	0	0
T92	0	22	0	0
T97	0	228	0	0
T149	0	20	0	0
T150	0	614	0	0
T151	0	11	0	0
T152	0	321	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16205928	350273	0	0
T1	27306	2215	0	0
T2	15959	276	0	0
T3	4211	0	0	0
T4	813	0	0	0
T5	19041	1035	0	0
T6	7806	0	0	0
T7	2269	0	0	0
T8	18948	1274	0	0
T9	2603	0	0	0
T10	2566	0	0	0
T13	0	217	0	0
T14	0	3277	0	0
T22	0	3166	0	0
T23	0	826	0	0
T27	0	88	0	0
T32	0	4059	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16205928	15671056	0	0
T1	27306	9582	0	0
T2	15959	15816	0	0
T3	4211	4129	0	0
T4	813	686	0	0
T5	19041	18661	0	0
T6	7806	6793	0	0
T7	2269	2204	0	0
T8	18948	18892	0	0
T9	2603	2410	0	0
T10	2566	2510	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16205928	143405	0	0
T1	27306	17572	0	0
T2	15959	0	0	0
T3	4211	0	0	0
T4	813	0	0	0
T5	19041	273	0	0
T6	7806	0	0	0
T7	2269	0	0	0
T8	18948	0	0	0
T9	2603	0	0	0
T10	2566	0	0	0
T13	0	271	0	0
T22	0	1715	0	0
T27	0	595	0	0
T97	0	874	0	0
T149	0	749	0	0
T150	0	1069	0	0
T153	0	2188	0	0
T154	0	1261	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16205928	2940	0	0
T4	813	1	0	0
T5	19041	0	0	0
T6	7806	6	0	0
T7	2269	0	0	0
T8	18948	0	0	0
T9	2603	6	0	0
T10	2566	0	0	0
T11	763	1	0	0
T12	0	1	0	0
T13	0	2	0	0
T14	0	43	0	0
T19	0	20	0	0
T22	42547	0	0	0
T23	0	14	0	0
T35	0	5	0	0
T36	1063	0	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16205928	180	0	0
T18	1329	0	0	0
T19	15474	40	0	0
T20	0	40	0	0
T21	0	20	0	0
T25	0	40	0	0
T26	0	40	0	0
T27	1496	0	0	0
T28	1132	0	0	0
T29	15717	0	0	0
T30	4880	0	0	0
T31	11908	0	0	0
T32	56300	0	0	0
T33	4459	0	0	0
T34	1478	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16205928	2940	0	0
T4	813	1	0	0
T5	19041	0	0	0
T6	7806	6	0	0
T7	2269	0	0	0
T8	18948	0	0	0
T9	2603	6	0	0
T10	2566	0	0	0
T11	763	1	0	0
T12	0	1	0	0
T13	0	2	0	0
T14	0	43	0	0
T19	0	20	0	0
T22	42547	0	0	0
T23	0	14	0	0
T35	0	5	0	0
T36	1063	0	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16205928	700558	0	0
T1	27306	2877	0	0
T2	15959	1669	0	0
T3	4211	0	0	0
T4	813	0	0	0
T5	19041	1547	0	0
T6	7806	169	0	0
T7	2269	0	0	0
T8	18948	1804	0	0
T9	2603	213	0	0
T10	2566	0	0	0
T13	0	157	0	0
T22	0	3734	0	0
T23	0	3920	0	0
T38	0	11	0	0