Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	375924	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

150630

1

T1

196

T5

10

T6

651

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	277058	1			T1	418		T2	1		T3	1
values[0x0]	123962	1			T1	229		T5	5		T6	631
values[0x1]	125534	1			T1	223		T5	5		T6	672

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	297485	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

229069

1

T1

345

T5

14

T6

1121

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1568	1			T1	3		T6	7		T10	3
valid_sources[0x01]	2753	1			T6	14		T10	18		T35	4
valid_sources[0x02]	3018	1			T6	19		T8	6		T10	16
valid_sources[0x03]	1808	1			T1	10		T6	17		T10	10
valid_sources[0x04]	1712	1			T1	4		T6	8		T7	36
valid_sources[0x05]	1534	1			T6	13		T10	4		T35	1
valid_sources[0x06]	1494	1			T6	2		T10	2		T36	3
valid_sources[0x07]	1664	1			T1	2		T6	8		T10	12
valid_sources[0x08]	1790	1			T6	7		T10	45		T43	3
valid_sources[0x09]	2903	1			T1	7		T6	14		T10	18
valid_sources[0x0a]	1666	1			T6	14		T7	13		T10	4
valid_sources[0x0b]	2597	1			T1	4		T6	7		T10	16
valid_sources[0x0c]	2435	1			T1	3		T6	10		T35	2
valid_sources[0x0d]	1523	1			T1	2		T6	14		T10	11
valid_sources[0x0e]	1706	1			T6	15		T7	10		T10	17
valid_sources[0x0f]	1998	1			T1	10		T6	12		T7	28
valid_sources[0x10]	1948	1			T6	13		T10	11		T35	7
valid_sources[0x11]	1752	1			T6	7		T10	7		T39	1
valid_sources[0x12]	2992	1			T6	15		T10	13		T36	3
valid_sources[0x13]	2585	1			T1	2		T6	10		T10	8
valid_sources[0x14]	1616	1			T6	8		T10	7		T35	1
valid_sources[0x15]	1558	1			T6	16		T39	2		T35	2
valid_sources[0x16]	1682	1			T1	2		T6	13		T10	8
valid_sources[0x17]	5126	1			T1	5		T6	4		T10	12
valid_sources[0x18]	2653	1			T1	6		T5	32		T6	11
valid_sources[0x19]	1591	1			T6	3		T10	17		T39	1
valid_sources[0x1a]	1650	1			T1	4		T6	15		T10	7
valid_sources[0x1b]	1550	1			T6	15		T10	3		T39	1
valid_sources[0x1c]	1535	1			T1	1		T6	7		T10	2
valid_sources[0x1d]	1779	1			T6	13		T7	32		T10	16
valid_sources[0x1e]	2053	1			T6	19		T10	16		T39	1
valid_sources[0x1f]	1539	1			T6	15		T10	10		T35	3
valid_sources[0x20]	1605	1			T6	12		T8	5		T10	23
valid_sources[0x21]	1951	1			T6	5		T35	8		T36	1
valid_sources[0x22]	1676	1			T1	1		T6	8		T10	11
valid_sources[0x23]	1921	1			T1	11		T6	9		T10	7
valid_sources[0x24]	1819	1			T6	12		T10	5		T42	7
valid_sources[0x25]	1590	1			T6	20		T10	7		T35	3
valid_sources[0x26]	1626	1			T6	16		T10	12		T35	2
valid_sources[0x27]	1454	1			T1	30		T6	13		T35	4
valid_sources[0x28]	1638	1			T1	16		T6	11		T10	4
valid_sources[0x29]	1912	1			T1	3		T6	8		T8	7
valid_sources[0x2a]	2550	1			T1	1		T6	8		T42	4
valid_sources[0x2b]	2615	1			T6	9		T10	2		T43	7
valid_sources[0x2c]	1371	1			T6	11		T10	21		T35	4
valid_sources[0x2d]	1677	1			T6	7		T35	4		T36	1
valid_sources[0x2e]	1595	1			T6	12		T39	1		T35	2
valid_sources[0x2f]	1791	1			T6	8		T7	18		T10	10
valid_sources[0x30]	1782	1			T6	9		T10	6		T35	6
valid_sources[0x31]	2023	1			T6	12		T8	10		T10	20
valid_sources[0x32]	1560	1			T1	3		T6	18		T10	16
valid_sources[0x33]	1891	1			T6	5		T10	7		T35	4
valid_sources[0x34]	2726	1			T1	1		T6	18		T10	11
valid_sources[0x35]	1694	1			T6	12		T10	9		T35	2
valid_sources[0x36]	1619	1			T6	7		T7	39		T10	2
valid_sources[0x37]	1637	1			T6	14		T10	2		T39	2
valid_sources[0x38]	3550	1			T6	12		T7	6		T10	11
valid_sources[0x39]	2008	1			T6	12		T10	13		T35	1
valid_sources[0x3a]	3218	1			T1	1		T6	14		T7	7
valid_sources[0x3b]	1845	1			T1	1		T6	18		T10	26
valid_sources[0x3c]	1576	1			T1	2		T6	11		T10	12
valid_sources[0x3d]	2766	1			T6	10		T10	22		T39	1
valid_sources[0x3e]	1844	1			T1	12		T6	9		T10	2
valid_sources[0x3f]	1586	1			T6	7		T10	4		T35	2
valid_sources[0x40]	2454	1			T6	10		T10	6		T39	1
valid_sources[0x41]	2240	1			T6	16		T7	36		T10	3
valid_sources[0x42]	1808	1			T1	5		T6	15		T10	3
valid_sources[0x43]	1635	1			T1	1		T6	7		T10	8
valid_sources[0x44]	1603	1			T6	9		T10	1		T35	4
valid_sources[0x45]	1680	1			T6	15		T10	12		T35	4
valid_sources[0x46]	2471	1			T1	5		T6	9		T10	3
valid_sources[0x47]	3659	1			T6	7		T7	11		T10	1
valid_sources[0x48]	2577	1			T6	18		T10	2		T39	1
valid_sources[0x49]	1496	1			T1	3		T6	10		T10	10
valid_sources[0x4a]	1859	1			T6	10		T10	1		T35	1
valid_sources[0x4b]	1613	1			T1	5		T6	17		T10	12
valid_sources[0x4c]	1653	1			T6	4		T10	5		T39	1
valid_sources[0x4d]	1546	1			T6	14		T10	9		T35	3
valid_sources[0x4e]	2569	1			T6	9		T8	7		T10	5
valid_sources[0x4f]	1565	1			T1	2		T6	16		T10	18
valid_sources[0x50]	1718	1			T1	1		T6	9		T10	9
valid_sources[0x51]	1655	1			T1	15		T6	14		T10	4
valid_sources[0x52]	2294	1			T1	16		T6	10		T10	1
valid_sources[0x53]	1597	1			T1	12		T6	10		T10	4
valid_sources[0x54]	1522	1			T6	5		T10	14		T39	1
valid_sources[0x55]	2601	1			T1	16		T6	11		T10	4
valid_sources[0x56]	1931	1			T6	11		T10	20		T39	1
valid_sources[0x57]	1502	1			T1	11		T6	14		T10	25
valid_sources[0x58]	1580	1			T6	12		T10	8		T35	7
valid_sources[0x59]	2140	1			T6	17		T7	19		T10	1
valid_sources[0x5a]	1572	1			T1	6		T6	6		T7	45
valid_sources[0x5b]	1896	1			T6	5		T10	16		T35	4
valid_sources[0x5c]	1704	1			T1	1		T6	23		T10	5
valid_sources[0x5d]	1858	1			T6	8		T7	78		T10	9
valid_sources[0x5e]	1774	1			T6	12		T10	5		T39	2
valid_sources[0x5f]	1882	1			T6	11		T10	2		T35	1
valid_sources[0x60]	2004	1			T1	11		T6	8		T10	14
valid_sources[0x61]	3744	1			T6	11		T10	8		T35	4
valid_sources[0x62]	1575	1			T1	4		T6	14		T10	10
valid_sources[0x63]	1481	1			T6	11		T10	3		T35	3
valid_sources[0x64]	2485	1			T6	9		T10	5		T39	1
valid_sources[0x65]	3841	1			T1	2		T6	8		T10	8
valid_sources[0x66]	2281	1			T1	3		T6	9		T10	3
valid_sources[0x67]	1780	1			T1	13		T6	4		T10	11
valid_sources[0x68]	1459	1			T6	7		T10	2		T39	1
valid_sources[0x69]	4342	1			T6	9		T10	2		T35	2
valid_sources[0x6a]	1735	1			T1	1		T6	10		T10	10
valid_sources[0x6b]	1643	1			T1	12		T6	15		T10	12
valid_sources[0x6c]	1988	1			T6	12		T10	10		T35	4
valid_sources[0x6d]	2054	1			T6	13		T7	13		T10	7
valid_sources[0x6e]	1626	1			T6	8		T10	12		T35	6
valid_sources[0x6f]	2054	1			T6	15		T10	4		T39	1
valid_sources[0x70]	2270	1			T6	19		T7	32		T10	13
valid_sources[0x71]	1801	1			T1	11		T6	10		T39	2
valid_sources[0x72]	2045	1			T6	20		T10	13		T39	1
valid_sources[0x73]	2004	1			T1	3		T6	11		T8	3
valid_sources[0x74]	1501	1			T6	10		T39	1		T35	5
valid_sources[0x75]	2025	1			T6	12		T39	1		T35	11
valid_sources[0x76]	1721	1			T1	5		T6	6		T10	7
valid_sources[0x77]	1644	1			T1	12		T6	11		T10	1
valid_sources[0x78]	2798	1			T3	1		T6	9		T10	22
valid_sources[0x79]	1710	1			T6	5		T10	10		T35	2
valid_sources[0x7a]	1777	1			T6	10		T10	14		T35	1
valid_sources[0x7b]	1816	1			T6	11		T10	2		T35	9
valid_sources[0x7c]	1706	1			T6	16		T7	34		T10	16
valid_sources[0x7d]	3886	1			T6	14		T10	2		T39	1
valid_sources[0x7e]	1512	1			T6	6		T10	2		T35	4
valid_sources[0x7f]	1609	1			T1	3		T6	18		T10	6
valid_sources[0x80]	2176	1			T1	39		T6	10		T10	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

76182

1

T1

87

T5

9

T6

297

values[0x0]

all_enables

biggest_size

47403

1

T1

70

T6

222

T7

76

values[0x1]

all_enables

biggest_size

27045

1

T1

39

T5

1

T6

132