SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35002 | 1 | T1 | 388 | T7 | 284 | T35 | 392 | ||||
others[1] | 34894 | 1 | T1 | 386 | T7 | 295 | T35 | 392 | ||||
others[2] | 35071 | 1 | T1 | 400 | T7 | 287 | T35 | 381 | ||||
others[3] | 58502 | 1 | T1 | 694 | T7 | 531 | T35 | 696 | ||||
false | 13855 | 1 | T1 | 50 | T6 | 74 | T7 | 50 | ||||
true | 22411 | 1 | T1 | 102 | T2 | 2 | T3 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35095 | 1 | T1 | 385 | T7 | 297 | T35 | 401 | ||||
others[1] | 34920 | 1 | T1 | 409 | T7 | 306 | T35 | 369 | ||||
others[2] | 35033 | 1 | T1 | 414 | T7 | 315 | T35 | 411 | ||||
others[3] | 58526 | 1 | T1 | 664 | T7 | 483 | T35 | 683 | ||||
false | 9547 | 1 | T1 | 50 | T6 | 37 | T7 | 50 | ||||
true | 18178 | 1 | T1 | 102 | T2 | 2 | T3 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 558 | 1 | T6 | 3 | T8 | 1 | T10 | 1 | ||||
others[1] | 556 | 1 | T6 | 6 | T10 | 1 | T21 | 1 | ||||
others[2] | 545 | 1 | T6 | 1 | T10 | 2 | T37 | 1 | ||||
others[3] | 935 | 1 | T6 | 4 | T8 | 1 | T10 | 3 | ||||
false | 10386 | 1 | T1 | 2 | T2 | 2 | T3 | 3 | ||||
true | 2792 | 1 | T6 | 31 | T8 | 2 | T10 | 14 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |