Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T13,T44

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	16796164	4769	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	16796164	201030	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	16796164	6775282	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	16796164	201054	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	16796164	4769	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	16796164	201030	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	16796164	6775282	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	16796164	201054	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16796164	4769	0	0
T1	31793	25	0	0
T2	584	0	0	0
T3	1059	0	0	0
T4	1668	0	0	0
T5	1017	1	0	0
T6	40006	12	0	0
T7	60591	26	0	0
T8	2039	0	0	0
T9	2246	1	0	0
T10	46369	15	0	0
T13	0	10	0	0
T35	0	23	0	0
T36	0	19	0	0
T44	0	1	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16796164	201030	0	0
T1	31793	958	0	0
T2	584	0	0	0
T3	1059	0	0	0
T4	1668	0	0	0
T5	1017	11	0	0
T6	40006	206	0	0
T7	60591	1941	0	0
T8	2039	0	0	0
T9	2246	12	0	0
T10	46369	228	0	0
T13	0	208	0	0
T35	0	520	0	0
T36	0	963	0	0
T44	0	61	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16796164	6775282	0	0
T1	31793	16434	0	0
T2	584	0	0	0
T3	1059	0	0	0
T4	1668	0	0	0
T5	1017	788	0	0
T6	40006	13457	0	0
T7	60591	31708	0	0
T8	2039	0	0	0
T9	2246	1392	0	0
T10	46369	23220	0	0
T35	0	10462	0	0
T39	0	3598	0	0
T42	0	1439	0	0
T43	0	2287	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16796164	201054	0	0
T1	31793	958	0	0
T2	584	0	0	0
T3	1059	0	0	0
T4	1668	0	0	0
T5	1017	11	0	0
T6	40006	206	0	0
T7	60591	1941	0	0
T8	2039	0	0	0
T9	2246	12	0	0
T10	46369	228	0	0
T13	0	208	0	0
T35	0	520	0	0
T36	0	963	0	0
T44	0	61	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16796164	4769	0	0
T1	31793	25	0	0
T2	584	0	0	0
T3	1059	0	0	0
T4	1668	0	0	0
T5	1017	1	0	0
T6	40006	12	0	0
T7	60591	26	0	0
T8	2039	0	0	0
T9	2246	1	0	0
T10	46369	15	0	0
T13	0	10	0	0
T35	0	23	0	0
T36	0	19	0	0
T44	0	1	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16796164	201030	0	0
T1	31793	958	0	0
T2	584	0	0	0
T3	1059	0	0	0
T4	1668	0	0	0
T5	1017	11	0	0
T6	40006	206	0	0
T7	60591	1941	0	0
T8	2039	0	0	0
T9	2246	12	0	0
T10	46369	228	0	0
T13	0	208	0	0
T35	0	520	0	0
T36	0	963	0	0
T44	0	61	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16796164	6775282	0	0
T1	31793	16434	0	0
T2	584	0	0	0
T3	1059	0	0	0
T4	1668	0	0	0
T5	1017	788	0	0
T6	40006	13457	0	0
T7	60591	31708	0	0
T8	2039	0	0	0
T9	2246	1392	0	0
T10	46369	23220	0	0
T35	0	10462	0	0
T39	0	3598	0	0
T42	0	1439	0	0
T43	0	2287	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16796164	201054	0	0
T1	31793	958	0	0
T2	584	0	0	0
T3	1059	0	0	0
T4	1668	0	0	0
T5	1017	11	0	0
T6	40006	206	0	0
T7	60591	1941	0	0
T8	2039	0	0	0
T9	2246	12	0	0
T10	46369	228	0	0
T13	0	208	0	0
T35	0	520	0	0
T36	0	963	0	0
T44	0	61	0	0