Unified Coverage Report :: Module :: pwrmgr_wake_info

Module : pwrmgr_wake_info

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_pwrmgr_component_0.1/rtl/pwrmgr_wake_info.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i_wake_info	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.i_wake_info

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_wake_info

	Line No.	Total	Covered	Percent
TOTAL		20	20	100.00
ALWAYS	29	3	3	100.00
CONT_ASSIGN	36	1	1	100.00
ALWAYS	42	6	6	100.00
ALWAYS	57	7	7	100.00
CONT_ASSIGN	68	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	70	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_pwrmgr_component_0.1/rtl/pwrmgr_wake_info.sv' or '../src/lowrisc_ip_pwrmgr_component_0.1/rtl/pwrmgr_wake_info.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
36	1	1
42	1	1
43	1	1
44	1	1
47	1	1
48	1	1
51	1	1
			MISSING_ELSE
57	1	1
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
63	1	1
			MISSING_ELSE
68	1	1
69	1	1
70	1	1

---

Cond Coverage for Module : pwrmgr_wake_info

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       36
 EXPRESSION (start_capture_i & ((~start_capture_q1)))
             -------1-------   ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T6

 LINE       44
 EXPRESSION (start_capture && ((!record_dis_i)))
             ------1------    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T10,T39
1	1	Covered	T1,T5,T6

 LINE       48
 EXPRESSION (record_dis_i && record_en)
             ------1-----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

---

Branch Coverage for Module : pwrmgr_wake_info

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
IF	29	2	2	100.00
IF	42	4	4	100.00
IF	57	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_pwrmgr_component_0.1/rtl/pwrmgr_wake_info.sv' or '../src/lowrisc_ip_pwrmgr_component_0.1/rtl/pwrmgr_wake_info.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	29	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	42	if ((!rst_ni))
-2-:	44	if ((start_capture && (!record_dis_i)))
-3-:	48	if ((record_dis_i && record_en))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T5,T6
0	0	1	Covered	T1,T5,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	57	if ((!rst_ni))
-2-:	59	if (wr_i)
-3-:	61	if (record_en)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T5,T6
0	0	1	Covered	T1,T5,T6
0	0	0	Covered	T1,T2,T3