Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	17419885	16868	0	0
intr_enable_rd_A	17419885	27903	0	0
reset_en_rd_A	17419885	1285	0	0
reset_en_regwen_rd_A	17419885	1137	0	0
wake_info_capture_dis_rd_A	17419885	1126	0	0
wakeup_en_rd_A	17419885	1957	0	0
wakeup_en_regwen_rd_A	17419885	1163	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17419885	16868	0	0
T11	2412	0	0	0
T13	54843	3	0	0
T14	2690	0	0	0
T19	0	36	0	0
T20	0	9	0	0
T22	21899	0	0	0
T23	6327	0	0	0
T44	1731	0	0	0
T53	0	115	0	0
T62	5115	0	0	0
T82	0	21	0	0
T83	0	7	0	0
T98	0	11	0	0
T99	0	3	0	0
T130	0	17	0	0
T131	0	31	0	0
T132	3669	0	0	0
T133	5703	0	0	0
T134	13227	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17419885	27903	0	0
T7	60591	178	0	0
T8	2039	0	0	0
T9	2246	10	0	0
T10	46369	331	0	0
T13	0	538	0	0
T23	0	28	0	0
T35	18626	0	0	0
T36	62564	173	0	0
T39	5315	33	0	0
T40	3039	0	0	0
T42	1888	20	0	0
T43	3146	0	0	0
T62	0	34	0	0
T81	0	76	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17419885	1285	0	0
T11	2412	0	0	0
T13	54843	15	0	0
T14	2690	0	0	0
T19	0	9	0	0
T20	0	12	0	0
T22	21899	0	0	0
T23	6327	0	0	0
T44	1731	0	0	0
T50	0	28	0	0
T62	5115	0	0	0
T82	0	10	0	0
T83	0	15	0	0
T86	0	17	0	0
T98	0	23	0	0
T99	0	20	0	0
T132	3669	0	0	0
T133	5703	0	0	0
T134	13227	0	0	0
T135	0	20	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17419885	1137	0	0
T11	2412	0	0	0
T13	54843	14	0	0
T14	2690	0	0	0
T19	0	16	0	0
T20	0	10	0	0
T22	21899	0	0	0
T23	6327	0	0	0
T44	1731	0	0	0
T50	0	30	0	0
T62	5115	0	0	0
T82	0	20	0	0
T83	0	24	0	0
T86	0	30	0	0
T98	0	25	0	0
T99	0	12	0	0
T132	3669	0	0	0
T133	5703	0	0	0
T134	13227	0	0	0
T135	0	11	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17419885	1126	0	0
T11	2412	0	0	0
T13	54843	11	0	0
T14	2690	0	0	0
T19	0	1	0	0
T20	0	16	0	0
T22	21899	0	0	0
T23	6327	0	0	0
T44	1731	0	0	0
T50	0	39	0	0
T62	5115	0	0	0
T82	0	9	0	0
T83	0	26	0	0
T86	0	25	0	0
T98	0	18	0	0
T99	0	18	0	0
T132	3669	0	0	0
T133	5703	0	0	0
T134	13227	0	0	0
T135	0	11	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17419885	1957	0	0
T11	2412	0	0	0
T13	54843	15	0	0
T14	2690	0	0	0
T19	0	3	0	0
T20	0	18	0	0
T22	21899	0	0	0
T23	6327	0	0	0
T44	1731	0	0	0
T50	0	28	0	0
T62	5115	0	0	0
T82	0	6	0	0
T83	0	27	0	0
T86	0	41	0	0
T98	0	25	0	0
T99	0	9	0	0
T132	3669	0	0	0
T133	5703	0	0	0
T134	13227	0	0	0
T135	0	19	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17419885	1163	0	0
T11	2412	0	0	0
T13	54843	11	0	0
T14	2690	0	0	0
T19	0	1	0	0
T20	0	19	0	0
T22	21899	0	0	0
T23	6327	0	0	0
T44	1731	0	0	0
T50	0	25	0	0
T62	5115	0	0	0
T82	0	27	0	0
T83	0	20	0	0
T86	0	29	0	0
T98	0	22	0	0
T99	0	8	0	0
T132	3669	0	0	0
T133	5703	0	0	0
T134	13227	0	0	0
T135	0	7	0	0