Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	50388492	104682	0	0
StatusRise_A	50388492	117485	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50388492	104682	0	0
T1	95379	224	0	0
T2	1752	3	0	0
T3	3177	0	0	0
T4	5004	0	0	0
T5	3051	6	0	0
T6	120018	626	0	0
T7	181773	211	0	0
T8	6117	21	0	0
T9	6738	6	0	0
T10	139107	519	0	0
T39	0	25	0	0
T42	0	14	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50388492	117485	0	0
T1	95379	230	0	0
T2	1752	9	0	0
T3	3177	9	0	0
T4	5004	12	0	0
T5	3051	9	0	0
T6	120018	677	0	0
T7	181773	216	0	0
T8	6117	24	0	0
T9	6738	9	0	0
T10	139107	566	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	16796164	38957	0	0
StatusRise_A	16796164	43544	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16796164	38957	0	0
T1	31793	89	0	0
T2	584	1	0	0
T3	1059	0	0	0
T4	1668	0	0	0
T5	1017	2	0	0
T6	40006	226	0	0
T7	60591	85	0	0
T8	2039	7	0	0
T9	2246	2	0	0
T10	46369	188	0	0
T39	0	10	0	0
T42	0	5	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16796164	43544	0	0
T1	31793	91	0	0
T2	584	3	0	0
T3	1059	3	0	0
T4	1668	4	0	0
T5	1017	3	0	0
T6	40006	244	0	0
T7	60591	87	0	0
T8	2039	8	0	0
T9	2246	3	0	0
T10	46369	206	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	16796164	38957	0	0
StatusRise_A	16796164	43545	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16796164	38957	0	0
T1	31793	89	0	0
T2	584	1	0	0
T3	1059	0	0	0
T4	1668	0	0	0
T5	1017	2	0	0
T6	40006	226	0	0
T7	60591	85	0	0
T8	2039	7	0	0
T9	2246	2	0	0
T10	46369	188	0	0
T39	0	10	0	0
T42	0	5	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16796164	43545	0	0
T1	31793	91	0	0
T2	584	3	0	0
T3	1059	3	0	0
T4	1668	4	0	0
T5	1017	3	0	0
T6	40006	244	0	0
T7	60591	87	0	0
T8	2039	8	0	0
T9	2246	3	0	0
T10	46369	206	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	16796164	26768	0	0
StatusRise_A	16796164	30396	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16796164	26768	0	0
T1	31793	46	0	0
T2	584	1	0	0
T3	1059	0	0	0
T4	1668	0	0	0
T5	1017	2	0	0
T6	40006	174	0	0
T7	60591	41	0	0
T8	2039	7	0	0
T9	2246	2	0	0
T10	46369	143	0	0
T39	0	5	0	0
T42	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16796164	30396	0	0
T1	31793	48	0	0
T2	584	3	0	0
T3	1059	3	0	0
T4	1668	4	0	0
T5	1017	3	0	0
T6	40006	189	0	0
T7	60591	42	0	0
T8	2039	8	0	0
T9	2246	3	0	0
T10	46369	154	0	0