Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	16796756	11237	0	0
EscTimeoutStoppedByClReset_A	16796164	2353508	0	0
EscTimeoutTriggersReset_A	3667877	404	0	0
RomAllowActiveState_A	16796164	43137	0	0
RomAllowCheckGoodState_A	16796164	43187	0	0
RomBlockActiveState_A	16796164	32619	0	0
RomBlockCheckGoodState_A	16796164	381779	0	0
RomIntgChkDisFalse_A	16796164	16265247	0	0
RomIntgChkDisTrue_A	16796164	122766	0	0
RstreqChkEsctimeout_A	16796164	3141	0	0
RstreqChkFsmterm_A	16796164	180	0	0
RstreqChkGlbesc_A	16796164	3141	0	0
RstreqChkMainpd_A	16796164	742439	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16796756	11237	0	0
T11	2413	33	0	0
T12	0	80	0	0
T14	2691	0	0	0
T15	3231	0	0	0
T19	31752	0	0	0
T22	21900	0	0	0
T41	3537	0	0	0
T44	1731	0	0	0
T92	0	307	0	0
T134	13228	0	0	0
T137	0	19	0	0
T138	0	115	0	0
T139	0	81	0	0
T140	0	14	0	0
T141	0	152	0	0
T142	0	25	0	0
T143	0	3	0	0
T144	17939	0	0	0
T145	4862	0	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16796164	2353508	0	0
T1	31793	5746	0	0
T2	584	37	0	0
T3	1059	38	0	0
T4	1668	40	0	0
T5	1017	23	0	0
T6	40006	5621	0	0
T7	60591	11408	0	0
T8	2039	133	0	0
T9	2246	12	0	0
T10	46369	3025	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3667877	404	0	0
T2	376	5	0	0
T3	241	0	0	0
T4	306	0	0	0
T5	442	0	0	0
T6	28000	0	0	0
T7	6092	0	0	0
T8	312	0	0	0
T9	201	0	0	0
T10	32992	0	0	0
T11	0	3	0	0
T12	0	4	0	0
T39	1197	0	0	0
T92	0	4	0	0
T137	0	2	0	0
T138	0	6	0	0
T146	0	3	0	0
T147	0	2	0	0
T148	0	2	0	0
T149	0	6	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16796164	43137	0	0
T1	31793	91	0	0
T2	584	3	0	0
T3	1059	3	0	0
T4	1668	4	0	0
T5	1017	3	0	0
T6	40006	244	0	0
T7	60591	87	0	0
T8	2039	8	0	0
T9	2246	3	0	0
T10	46369	206	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16796164	43187	0	0
T1	31793	91	0	0
T2	584	3	0	0
T3	1059	3	0	0
T4	1668	4	0	0
T5	1017	3	0	0
T6	40006	244	0	0
T7	60591	87	0	0
T8	2039	8	0	0
T9	2246	3	0	0
T10	46369	206	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16796164	32619	0	0
T13	54843	0	0	0
T21	1835	236	0	0
T22	0	27	0	0
T23	6327	1084	0	0
T35	18626	9	0	0
T36	62564	0	0	0
T37	1991	0	0	0
T38	0	788	0	0
T40	3039	0	0	0
T62	5115	0	0	0
T81	7450	0	0	0
T132	3669	0	0	0
T150	0	1247	0	0
T151	0	706	0	0
T152	0	3	0	0
T153	0	243	0	0
T154	0	720	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16796164	381779	0	0
T1	31793	2370	0	0
T2	584	0	0	0
T3	1059	0	0	0
T4	1668	0	0	0
T5	1017	0	0	0
T6	40006	849	0	0
T7	60591	4190	0	0
T8	2039	0	0	0
T9	2246	0	0	0
T10	46369	528	0	0
T13	0	518	0	0
T21	0	116	0	0
T22	0	1303	0	0
T23	0	893	0	0
T35	0	1291	0	0
T36	0	4095	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16796164	16265247	0	0
T1	31793	31656	0	0
T2	584	456	0	0
T3	1059	853	0	0
T4	1668	1409	0	0
T5	1017	959	0	0
T6	40006	38670	0	0
T7	60591	58189	0	0
T8	2039	1989	0	0
T9	2246	2173	0	0
T10	46369	45109	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16796164	122766	0	0
T7	60591	2232	0	0
T8	2039	0	0	0
T9	2246	0	0	0
T10	46369	0	0	0
T21	0	637	0	0
T22	0	692	0	0
T23	0	1988	0	0
T35	18626	0	0	0
T36	62564	0	0	0
T39	5315	0	0	0
T40	3039	0	0	0
T42	1888	0	0	0
T43	3146	0	0	0
T150	0	2253	0	0
T151	0	53	0	0
T152	0	7947	0	0
T154	0	1220	0	0
T155	0	530	0	0
T156	0	1357	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16796164	3141	0	0
T2	584	1	0	0
T3	1059	0	0	0
T4	1668	0	0	0
T5	1017	0	0	0
T6	40006	33	0	0
T7	60591	0	0	0
T8	2039	1	0	0
T9	2246	0	0	0
T10	46369	16	0	0
T11	0	1	0	0
T13	0	19	0	0
T21	0	3	0	0
T23	0	3	0	0
T37	0	2	0	0
T39	5315	0	0	0
T40	0	4	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16796164	180	0	0
T16	14074	20	0	0
T17	0	40	0	0
T18	0	40	0	0
T24	0	40	0	0
T25	0	40	0	0
T26	2366	0	0	0
T27	14317	0	0	0
T28	2493	0	0	0
T29	81490	0	0	0
T30	31124	0	0	0
T31	7066	0	0	0
T32	6578	0	0	0
T33	3965	0	0	0
T34	2886	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16796164	3141	0	0
T2	584	1	0	0
T3	1059	0	0	0
T4	1668	0	0	0
T5	1017	0	0	0
T6	40006	33	0	0
T7	60591	0	0	0
T8	2039	1	0	0
T9	2246	0	0	0
T10	46369	16	0	0
T11	0	1	0	0
T13	0	19	0	0
T21	0	3	0	0
T23	0	3	0	0
T37	0	2	0	0
T39	5315	0	0	0
T40	0	4	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16796164	742439	0	0
T1	31793	3506	0	0
T2	584	0	0	0
T3	1059	6	0	0
T4	1668	12	0	0
T5	1017	0	0	0
T6	40006	1208	0	0
T7	60591	7687	0	0
T8	2039	56	0	0
T9	2246	0	0	0
T10	46369	828	0	0
T21	0	48	0	0
T35	0	2024	0	0
T36	0	4171	0	0