Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	379667	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

147131

1

T1

1

T2

51

T3

1623

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	274314	1			T1	1		T2	81		T3	2941
values[0x0]	125906	1			T2	18		T3	1474		T4	431
values[0x1]	126578	1			T2	15		T3	1476		T4	371

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	300504	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

226294

1

T1

1

T2

58

T3

2495

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3257	1			T2	1		T3	19		T38	1
valid_sources[0x01]	1672	1			T3	17		T7	1		T69	1
valid_sources[0x02]	1995	1			T3	22		T4	336		T33	1
valid_sources[0x03]	1710	1			T3	23		T8	3		T33	2
valid_sources[0x04]	2169	1			T3	28		T38	2		T33	1
valid_sources[0x05]	1629	1			T3	31		T7	1		T33	1
valid_sources[0x06]	1813	1			T3	20		T69	1		T21	1
valid_sources[0x07]	1896	1			T3	26		T38	1		T69	2
valid_sources[0x08]	1663	1			T3	28		T8	7		T38	3
valid_sources[0x09]	1739	1			T3	25		T69	4		T33	3
valid_sources[0x0a]	2366	1			T3	28		T8	5		T38	2
valid_sources[0x0b]	2097	1			T3	21		T38	4		T33	1
valid_sources[0x0c]	1789	1			T3	27		T4	7		T112	2
valid_sources[0x0d]	5013	1			T2	2		T3	18		T113	3
valid_sources[0x0e]	1610	1			T3	14		T37	2		T69	3
valid_sources[0x0f]	1605	1			T3	22		T5	2		T7	2
valid_sources[0x10]	2216	1			T2	2		T3	20		T4	3
valid_sources[0x11]	1781	1			T3	24		T38	3		T112	1
valid_sources[0x12]	1910	1			T3	18		T38	1		T69	3
valid_sources[0x13]	2302	1			T3	22		T4	12		T38	1
valid_sources[0x14]	2815	1			T3	29		T5	1		T7	2
valid_sources[0x15]	2487	1			T3	25		T8	8		T38	1
valid_sources[0x16]	1817	1			T3	25		T4	25		T5	1
valid_sources[0x17]	1975	1			T3	19		T5	1		T8	2
valid_sources[0x18]	1664	1			T2	3		T3	17		T4	27
valid_sources[0x19]	1650	1			T3	30		T8	1		T38	2
valid_sources[0x1a]	1594	1			T3	17		T38	1		T113	2
valid_sources[0x1b]	2632	1			T3	21		T33	2		T35	12
valid_sources[0x1c]	1741	1			T3	14		T7	1		T37	2
valid_sources[0x1d]	2197	1			T3	26		T37	1		T112	1
valid_sources[0x1e]	1920	1			T2	4		T3	17		T37	1
valid_sources[0x1f]	1670	1			T3	20		T38	1		T33	2
valid_sources[0x20]	3258	1			T3	22		T112	3		T33	3
valid_sources[0x21]	2478	1			T3	18		T10	860		T37	1
valid_sources[0x22]	1872	1			T3	23		T7	1		T38	2
valid_sources[0x23]	1747	1			T3	24		T4	2		T38	1
valid_sources[0x24]	1864	1			T3	21		T38	1		T69	6
valid_sources[0x25]	1713	1			T2	3		T3	28		T38	2
valid_sources[0x26]	1753	1			T3	21		T8	1		T37	1
valid_sources[0x27]	2321	1			T3	26		T4	6		T33	3
valid_sources[0x28]	1922	1			T2	1		T3	27		T69	1
valid_sources[0x29]	2181	1			T3	15		T8	3		T38	1
valid_sources[0x2a]	1814	1			T3	22		T38	1		T112	5
valid_sources[0x2b]	1740	1			T3	25		T5	1		T38	2
valid_sources[0x2c]	1528	1			T3	18		T7	1		T112	4
valid_sources[0x2d]	1944	1			T3	15		T7	1		T38	2
valid_sources[0x2e]	1874	1			T3	23		T7	1		T38	1
valid_sources[0x2f]	1722	1			T2	1		T3	27		T38	2
valid_sources[0x30]	1659	1			T3	20		T8	1		T69	1
valid_sources[0x31]	1573	1			T3	21		T69	3		T21	5
valid_sources[0x32]	2559	1			T3	30		T38	1		T35	6
valid_sources[0x33]	1571	1			T2	1		T3	15		T7	1
valid_sources[0x34]	1756	1			T3	19		T4	2		T5	1
valid_sources[0x35]	1999	1			T3	21		T4	12		T37	1
valid_sources[0x36]	2315	1			T2	1		T3	22		T4	122
valid_sources[0x37]	1616	1			T3	25		T4	3		T37	1
valid_sources[0x38]	1702	1			T3	21		T7	1		T8	13
valid_sources[0x39]	1574	1			T3	20		T4	15		T38	2
valid_sources[0x3a]	1721	1			T3	31		T8	5		T38	1
valid_sources[0x3b]	1777	1			T3	18		T4	19		T112	5
valid_sources[0x3c]	2538	1			T3	31		T33	1		T113	2
valid_sources[0x3d]	1757	1			T3	35		T7	1		T8	1
valid_sources[0x3e]	1852	1			T3	27		T4	11		T37	1
valid_sources[0x3f]	1820	1			T3	39		T38	1		T112	3
valid_sources[0x40]	1604	1			T2	5		T3	25		T7	1
valid_sources[0x41]	1677	1			T3	27		T7	1		T37	1
valid_sources[0x42]	1711	1			T3	17		T38	2		T33	1
valid_sources[0x43]	1636	1			T3	21		T7	1		T37	1
valid_sources[0x44]	1723	1			T3	21		T7	1		T37	1
valid_sources[0x45]	1569	1			T3	27		T4	14		T7	2
valid_sources[0x46]	5841	1			T2	3		T3	22		T38	1
valid_sources[0x47]	1646	1			T3	17		T8	1		T37	1
valid_sources[0x48]	2053	1			T3	24		T35	18		T113	2
valid_sources[0x49]	1694	1			T1	1		T2	2		T3	22
valid_sources[0x4a]	1789	1			T3	23		T7	3		T113	3
valid_sources[0x4b]	1820	1			T3	25		T4	163		T38	3
valid_sources[0x4c]	1800	1			T3	19		T7	2		T38	3
valid_sources[0x4d]	1844	1			T3	24		T7	1		T37	1
valid_sources[0x4e]	1693	1			T3	30		T38	2		T113	1
valid_sources[0x4f]	2073	1			T3	27		T8	1		T112	1
valid_sources[0x50]	1690	1			T2	2		T3	30		T37	1
valid_sources[0x51]	1747	1			T3	28		T37	1		T38	2
valid_sources[0x52]	2012	1			T3	28		T7	2		T37	1
valid_sources[0x53]	1976	1			T3	15		T37	2		T38	1
valid_sources[0x54]	1814	1			T3	26		T7	1		T69	1
valid_sources[0x55]	2839	1			T3	27		T4	127		T37	1
valid_sources[0x56]	6876	1			T3	20		T113	5		T21	2
valid_sources[0x57]	1595	1			T3	22		T38	1		T33	2
valid_sources[0x58]	2383	1			T3	24		T35	10		T113	1
valid_sources[0x59]	2055	1			T3	32		T33	1		T113	1
valid_sources[0x5a]	1806	1			T2	1		T3	20		T5	1
valid_sources[0x5b]	1726	1			T2	3		T3	24		T8	4
valid_sources[0x5c]	1722	1			T2	1		T3	19		T33	1
valid_sources[0x5d]	1723	1			T3	18		T38	2		T112	1
valid_sources[0x5e]	2783	1			T3	28		T7	1		T112	10
valid_sources[0x5f]	2926	1			T3	24		T7	1		T69	8
valid_sources[0x60]	1616	1			T3	26		T33	1		T113	1
valid_sources[0x61]	2653	1			T3	17		T4	173		T8	1
valid_sources[0x62]	3350	1			T3	22		T7	1		T37	3
valid_sources[0x63]	1752	1			T3	29		T5	3		T7	1
valid_sources[0x64]	1747	1			T3	20		T5	2		T7	1
valid_sources[0x65]	1701	1			T3	20		T112	5		T35	15
valid_sources[0x66]	2513	1			T3	16		T38	1		T33	2
valid_sources[0x67]	1582	1			T2	2		T3	19		T8	12
valid_sources[0x68]	2156	1			T3	25		T4	41		T8	1
valid_sources[0x69]	1521	1			T3	25		T5	2		T8	5
valid_sources[0x6a]	1477	1			T2	3		T3	20		T38	1
valid_sources[0x6b]	2792	1			T3	29		T33	1		T113	1
valid_sources[0x6c]	1717	1			T2	2		T3	25		T5	1
valid_sources[0x6d]	1838	1			T3	21		T7	2		T38	1
valid_sources[0x6e]	1965	1			T2	1		T3	19		T37	2
valid_sources[0x6f]	2474	1			T2	2		T3	34		T38	1
valid_sources[0x70]	1747	1			T3	28		T4	37		T8	1
valid_sources[0x71]	5350	1			T3	22		T69	4		T35	1
valid_sources[0x72]	1604	1			T3	31		T37	1		T38	1
valid_sources[0x73]	1746	1			T3	23		T7	1		T69	3
valid_sources[0x74]	1941	1			T3	31		T4	8		T69	2
valid_sources[0x75]	2134	1			T3	20		T37	1		T38	2
valid_sources[0x76]	2056	1			T3	20		T4	96		T7	1
valid_sources[0x77]	2055	1			T2	3		T3	23		T4	27
valid_sources[0x78]	1885	1			T3	26		T112	1		T33	3
valid_sources[0x79]	1917	1			T3	22		T7	1		T37	2
valid_sources[0x7a]	1662	1			T3	23		T7	1		T8	3
valid_sources[0x7b]	1948	1			T2	1		T3	28		T38	1
valid_sources[0x7c]	2223	1			T3	24		T7	2		T38	1
valid_sources[0x7d]	1916	1			T3	28		T33	1		T113	1
valid_sources[0x7e]	1954	1			T3	15		T7	1		T38	1
valid_sources[0x7f]	2602	1			T3	16		T37	1		T38	1
valid_sources[0x80]	1897	1			T3	22		T113	2		T21	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

73368

1

T1

1

T2

41

T3

791

values[0x0]

all_enables

biggest_size

47292

1

T2

6

T3

515

T4

177

values[0x1]

all_enables

biggest_size

26471

1

T2

4

T3

317

T4

76