SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35020 | 1 | T10 | 366 | T35 | 385 | T20 | 306 | ||||
others[1] | 34834 | 1 | T10 | 394 | T35 | 403 | T20 | 310 | ||||
others[2] | 35080 | 1 | T3 | 1 | T10 | 380 | T35 | 405 | ||||
others[3] | 58360 | 1 | T3 | 2 | T10 | 726 | T35 | 660 | ||||
false | 14035 | 1 | T3 | 69 | T4 | 40 | T8 | 24 | ||||
true | 22861 | 1 | T1 | 2 | T2 | 13 | T3 | 132 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35051 | 1 | T3 | 1 | T10 | 393 | T35 | 405 | ||||
others[1] | 35060 | 1 | T10 | 369 | T35 | 398 | T20 | 305 | ||||
others[2] | 35157 | 1 | T3 | 2 | T10 | 388 | T35 | 397 | ||||
others[3] | 58128 | 1 | T3 | 2 | T10 | 719 | T35 | 656 | ||||
false | 9632 | 1 | T3 | 36 | T4 | 20 | T8 | 12 | ||||
true | 18497 | 1 | T1 | 2 | T2 | 13 | T3 | 98 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 604 | 1 | T3 | 6 | T4 | 3 | T7 | 1 | ||||
others[1] | 608 | 1 | T2 | 1 | T3 | 5 | T4 | 2 | ||||
others[2] | 592 | 1 | T3 | 3 | T4 | 2 | T7 | 1 | ||||
others[3] | 916 | 1 | T3 | 3 | T4 | 2 | T112 | 5 | ||||
false | 10914 | 1 | T1 | 2 | T2 | 22 | T3 | 118 | ||||
true | 2981 | 1 | T2 | 8 | T3 | 35 | T4 | 13 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |