Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	18535665	13541	0	0
intr_enable_rd_A	18535665	44427	0	0
reset_en_rd_A	18535665	2233	0	0
reset_en_regwen_rd_A	18535665	1893	0	0
wake_info_capture_dis_rd_A	18535665	1937	0	0
wakeup_en_rd_A	18535665	2981	0	0
wakeup_en_regwen_rd_A	18535665	2038	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18535665	13541	0	0
T3	303207	46	0	0
T4	84936	35	0	0
T5	840	0	0	0
T6	1742	0	0	0
T7	4720	0	0	0
T8	10877	0	0	0
T9	2204	0	0	0
T10	60891	0	0	0
T37	3961	0	0	0
T38	2614	0	0	0
T40	0	37	0	0
T72	0	69	0	0
T119	0	5	0	0
T120	0	4	0	0
T121	0	12	0	0
T122	0	17	0	0
T123	0	102	0	0
T124	0	10	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18535665	44427	0	0
T3	303207	1421	0	0
T4	84936	0	0	0
T5	840	0	0	0
T6	1742	0	0	0
T7	4720	0	0	0
T8	10877	0	0	0
T9	2204	0	0	0
T10	60891	179	0	0
T19	0	2368	0	0
T20	0	163	0	0
T36	0	17	0	0
T37	3961	0	0	0
T38	2614	0	0	0
T69	0	63	0	0
T71	0	42	0	0
T114	0	38	0	0
T119	0	2429	0	0
T125	0	11	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18535665	2233	0	0
T3	303207	30	0	0
T4	84936	0	0	0
T5	840	0	0	0
T6	1742	0	0	0
T7	4720	0	0	0
T8	10877	0	0	0
T9	2204	0	0	0
T10	60891	0	0	0
T19	0	12	0	0
T37	3961	0	0	0
T38	2614	0	0	0
T65	0	7	0	0
T73	0	42	0	0
T119	0	12	0	0
T120	0	4	0	0
T121	0	12	0	0
T122	0	7	0	0
T126	0	7	0	0
T127	0	20	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18535665	1893	0	0
T3	303207	45	0	0
T4	84936	0	0	0
T5	840	0	0	0
T6	1742	0	0	0
T7	4720	0	0	0
T8	10877	0	0	0
T9	2204	0	0	0
T10	60891	0	0	0
T19	0	3	0	0
T37	3961	0	0	0
T38	2614	0	0	0
T65	0	9	0	0
T73	0	27	0	0
T119	0	19	0	0
T121	0	9	0	0
T122	0	28	0	0
T126	0	9	0	0
T127	0	22	0	0
T128	0	1	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18535665	1937	0	0
T3	303207	23	0	0
T4	84936	0	0	0
T5	840	0	0	0
T6	1742	0	0	0
T7	4720	0	0	0
T8	10877	0	0	0
T9	2204	0	0	0
T10	60891	0	0	0
T19	0	14	0	0
T37	3961	0	0	0
T38	2614	0	0	0
T59	0	24	0	0
T65	0	11	0	0
T73	0	34	0	0
T119	0	15	0	0
T121	0	9	0	0
T122	0	10	0	0
T126	0	10	0	0
T127	0	22	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18535665	2981	0	0
T3	303207	41	0	0
T4	84936	0	0	0
T5	840	0	0	0
T6	1742	0	0	0
T7	4720	0	0	0
T8	10877	0	0	0
T9	2204	0	0	0
T10	60891	0	0	0
T19	0	5	0	0
T37	3961	0	0	0
T38	2614	0	0	0
T65	0	13	0	0
T73	0	24	0	0
T119	0	17	0	0
T121	0	10	0	0
T122	0	26	0	0
T126	0	2	0	0
T127	0	24	0	0
T128	0	2	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18535665	2038	0	0
T3	303207	43	0	0
T4	84936	0	0	0
T5	840	0	0	0
T6	1742	0	0	0
T7	4720	0	0	0
T8	10877	0	0	0
T9	2204	0	0	0
T10	60891	0	0	0
T37	3961	0	0	0
T38	2614	0	0	0
T59	0	21	0	0
T65	0	7	0	0
T73	0	40	0	0
T119	0	17	0	0
T121	0	4	0	0
T122	0	28	0	0
T126	0	7	0	0
T127	0	24	0	0
T128	0	2	0	0